| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 327 SADDSAT, enumerator
|
| D | TargetLowering.h | 2458 case ISD::SADDSAT: in isCommutativeBinOp()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2595 { ISD::SADDSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2596 { ISD::SADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2670 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2671 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2725 { ISD::SADDSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2726 { ISD::SADDSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2780 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2781 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2892 { ISD::SADDSAT, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2893 { ISD::SADDSAT, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
|
| D | X86ISelLowering.cpp | 961 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
965 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1362 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1366 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1689 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
30559 case ISD::SADDSAT: in LowerOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 452 case ISD::SADDSAT: in LegalizeOp()
850 case ISD::SADDSAT: in Expand()
|
| D | SelectionDAGDumper.cpp | 317 case ISD::SADDSAT: return "saddsat"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 170 case ISD::SADDSAT: in PromoteIntegerResult()
812 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
839 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
2213 case ISD::SADDSAT: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 129 case ISD::SADDSAT: in ScalarizeVectorResult()
1040 case ISD::SADDSAT: in SplitVectorResult()
3031 case ISD::SADDSAT: in WidenVectorResult()
|
| D | SelectionDAG.cpp | 5117 case ISD::SADDSAT: return C1.sadd_sat(C2); in FoldValue()
5632 case ISD::SADDSAT: in getNode()
5641 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
5995 case ISD::SADDSAT: in getNode()
|
| D | LegalizeDAG.cpp | 1136 case ISD::SADDSAT: in LegalizeOp()
3358 case ISD::SADDSAT: in ExpandNode()
|
| D | TargetLowering.cpp | 8025 case ISD::SADDSAT: in expandAddSubSat()
8396 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; in expandSADDSUBO()
|
| D | SelectionDAGBuilder.cpp | 6465 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
|
| D | DAGCombiner.cpp | 1613 case ISD::SADDSAT: in visit()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 778 setOperationAction(ISD::SADDSAT, VT, Expand); in initActions()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 211 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
269 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1109 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1111 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1119 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
4973 case ISD::SADDSAT: in LowerADDSUBSAT()
4989 case ISD::SADDSAT: in LowerADDSUBSAT()
10195 case ISD::SADDSAT: in LowerOperation()
10297 case ISD::SADDSAT: in ReplaceNodeResults()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 492 setOperationAction(ISD::SADDSAT, MVT::i16, Legal); in SITargetLowering()
494 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in SITargetLowering()
718 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal); in SITargetLowering()
749 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom); in SITargetLowering()
4616 case ISD::SADDSAT: in LowerOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 178 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 412 def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 519 setOperationAction(ISD::SADDSAT, VT, Legal); in RISCVTargetLowering()
750 setOperationAction(ISD::SADDSAT, VT, Custom); in RISCVTargetLowering()
2582 case ISD::SADDSAT: in LowerOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 325 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
1054 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
14456 return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true); in performIntrinsicCombine()
14464 return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 723 setOperationAction(ISD::SADDSAT, VT, Legal); in PPCTargetLowering()
|