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Searched refs:Rt (Results 1 – 25 of 39) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
28 (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
256 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
257 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
333 (MI RsPred:$Rs, RtPred:$Rt)>;
342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
717 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
718 (Output RsPred:$Rs, RtPred:$Rt)>;
721 : OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
DHexagonPatternsHVX.td109 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),
110 (MI I32:$Rt, imm:$Off)>;
111 def: Pat<(ResType (Load I32:$Rt)),
112 (MI I32:$Rt, 0)>;
136 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
137 (MI I32:$Rt, 0)>;
138 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
139 (MI I32:$Rt, imm:$Off)>;
174 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$Off)),
175 (MI I32:$Rt, imm:$Off, Value:$Vs)>;
[all …]
DHexagonPatternsV65.td12 (ins IntRegs:$_dst_, IntRegs:$Rt,
21 (ins IntRegs:$_dst_, IntRegs:$Rt,
30 (ins IntRegs:$_dst_, IntRegs:$Rt,
43 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
52 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
61 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
DHexagonAsmPrinter.cpp374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
375 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
376 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
386 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
387 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
398 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
61 //Rxx^=asr(Rss,Rt)
63 //Rxx^=asl(Rss,Rt)
65 //Rxx^=lsr(Rss,Rt)
67 //Rxx^=lsl(Rss,Rt)
[all …]
DHexagonBitTracker.cpp294 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt, in evaluate()
297 assert(Ws == Rt.width()); in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td1177 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
1178 opc, ".w\t$Rt, $addr",
1179 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
1181 bits<4> Rt;
1189 let Inst{15-12} = Rt;
1194 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1195 opc, "\t$Rt, $addr",
1196 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1198 bits<4> Rt;
1207 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td1996 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1997 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1998 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1999 bits<4> Rt;
2003 let Inst{15-12} = Rt;
2006 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
2007 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
2008 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2009 bits<4> Rt;
2014 let Inst{15-12} = Rt;
[all …]
DARMInstrVFP.td1144 (outs GPR:$Rt), (ins SPR:$Sn),
1145 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
1146 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1150 bits<4> Rt;
1156 let Inst{15-12} = Rt;
1168 (outs SPR:$Sn), (ins GPR:$Rt),
1169 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
1170 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1175 bits<4> Rt;
1180 let Inst{15-12} = Rt;
[all …]
DARMInstrThumb.td692 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
693 "ldr", "\t$Rt, $addr",
694 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
697 bits<3> Rt;
699 let Inst{10-8} = Rt;
706 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
707 "ldr", "\t$Rt, $addr",
708 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
710 bits<3> Rt;
712 let Inst{10-8} = Rt;
[all …]
DARMInstrFormats.td657 bits<4> Rt;
663 let Inst{15-12} = Rt;
672 bits<4> Rt;
681 let Inst{3-0} = Rt;
711 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
712 bits<4> Rt;
719 let Inst{15-12} = Rt;
783 bits<4> Rt;
789 let Inst{15-12} = Rt;
851 bits<4> Rt;
[all …]
DARMBaseInstrInfo.cpp3462 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3464 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3469 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3471 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3499 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3503 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3511 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3513 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3534 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
3535 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
680 if (Rs >= Rt) { in DecodeAddiGroupBranch()
683 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
694 Rt))); in DecodeAddiGroupBranch()
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
708 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
711 Rt))); in DecodePOP35GroupBranchMMR6()
715 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
720 Rt))); in DecodePOP35GroupBranchMMR6()
725 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
211 Rt = L.getOperand(0); in getCompoundInsn()
216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
256 CompoundInsn->addOperand(Rt); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1174 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1185 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
1195 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1202 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1206 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1210 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1214 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1218 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1222 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1235 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/xray/
Dxray_mips.cpp41 uint32_t Rt, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
Dxray_mips64.cpp42 uint32_t Rt, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1323 [(set GPR64:$Rt, (int_aarch64_tstart))]>;
1330 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
1783 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
1816 def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
1820 def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),
1821 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
1823 def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
1825 def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
1826 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
1827 def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
[all …]
DAArch64InstrFormats.td1326 // System instructions which do not have an Rt register.
1333 // System instructions which have an Rt register.
1338 bits<5> Rt;
1339 let Inst{4-0} = Rt;
1359 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1360 bits<5> Rt;
1361 let Inst{4-0} = Rt;
1368 : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
1499 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
1500 "mrs", "\t$Rt, $systemreg"> {
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1908 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
2006 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
2018 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2042 if (Rt == 15) in DecodeAddrMode3Instruction()
2044 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1392 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1395 TmpInst.addOperand(Rt); in processInstruction()
1396 TmpInst.addOperand(Rt); in processInstruction()
1813 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1814 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1819 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1824 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1833 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1834 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1839 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
140 Register Reg = Rs == GAReg ? Rt : Rs; in matchLargeOffset()
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp930 uint32_t Rt; // the source register in EmulatePUSH() local
949 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
951 if (BadReg(Rt)) in EmulatePUSH()
953 registers = (1u << Rt); in EmulatePUSH()
962 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
964 if (Rt == dwarf_sp) in EmulatePUSH()
966 registers = (1u << Rt); in EmulatePUSH()
1045 uint32_t Rt; // the destination register in EmulatePOP() local
1069 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1072 if (Rt == 13) in EmulatePOP()
[all …]
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
DEmulateInstructionARM64.cpp710 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP() local
713 integer t = UInt(Rt); in EmulateLDPSTP()
1120 integer t = UInt(Rt); in EmulateCBZ()
1158 integer t = UInt(Rt); in EmulateTBZ()

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