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Searched refs:Rn (Results 1 – 25 of 36) sorted by relevance

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/freebsd-12-stable/contrib/binutils/gas/doc/
Dc-sh.texi248 Rn @r{a numbered register}
255 add #imm,Rn lds.l @@Rn+,PR
256 add Rm,Rn mac.w @@Rm+,@@Rn+
257 addc Rm,Rn mov #imm,Rn
258 addv Rm,Rn mov Rm,Rn
259 and #imm,R0 mov.b Rm,@@(R0,Rn)
260 and Rm,Rn mov.b Rm,@@-Rn
261 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
264 bsr disp12 mov.b @@(R0,Rm),Rn
265 bt disp8 mov.b @@Rm+,Rn
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td754 def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn),
755 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>,
875 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
883 (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
910 (InputType RegType:$Rn))))];
1041 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
1042 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>;
1043 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
1044 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>;
1045 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
[all …]
DAArch64InstrFormats.td1645 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1646 bits<5> Rn;
1647 let Inst{9-5} = Rn;
1658 : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
1660 bits<5> Rn;
1664 let Inst{9-5} = Rn;
1679 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
1680 bits<5> Rn;
1684 let Inst{9-5} = Rn;
1689 : AuthBase<M, (outs), (ins GPR64:$Rn), asm, "\t$Rn", []> {
[all …]
DAArch64InstrAtomics.td47 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
49 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
52 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
53 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
55 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
57 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
58 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
62 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
64 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
[all …]
DAArch64SchedA64FX.td2307 // [ 5] "addpl $Rd, $Rn, $imm6";
2310 // [ 6] "addvl $Rd, $Rn, $imm6";
2508 // [72] "cpy $Zd, $Pg/m, $Rn";
2520 // [76] "ctermeq $Rn, $Rm";
2523 // [77] "ctermne $Rn, $Rm";
2553 // [87] "dup $Zd, $Rn";
2858 // [189] "index $Zd, $Rn, $Rm";
2861 // [190] "index $Zd, $Rn, $imm5";
2888 // [199] "ld1b $Zt, $Pg/z, [$Rn, $Rm]";
2891 // [200] "ld1b $Zt, $Pg/z, [$Rn, $Zm]";
[all …]
DSVEInstrFormats.td478 : Pat<(vt (op pt:$Pg, vt:$Rn, (vt (AArch64dup (it (cast i32:$imm)))))),
479 (inst $Pg, $Rn, i32:$imm)>;
484 : Pat<(vt (op (pt (SVEAllActive)), vt:$Rn, (vt (AArch64dup (it (cast i32:$imm)))))),
485 (inst $Rn, i32:$imm)>;
679 def : Pat<(i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))),
680 … (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
681 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))))),
682 … (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
684 def : Pat<(i32 (op GPR32:$Rn, (nxv8i1 PPRAny:$Pg))),
685 … (!cast<Instruction>(NAME # _H) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
[all …]
DSMEInstrFormats.td168 bits<5> Rn;
177 let Inst{9-5} = Rn;
188 (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
190 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
196 (ins MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn,
198 mnemonic, "\t\\{$ZAt[$Rv]\\}, $Pg/z, [$Rn, $Rm]">;
204 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
205 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
207 def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv, $imm]\\}, $Pg" # pg_suffix # ", [$Rn]",
208 … (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
[all …]
DAArch64InstrGISel.td245 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
246 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
247 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
459 bits<4> Rn;
471 bits<4> Rn;
474 let Inst{19-16} = Rn;
510 bits<4> Rn;
513 let Inst{19-16} = Rn;
543 bits<4> Rn;
546 let Inst{19-16} = Rn;
555 bits<4> Rn;
[all …]
DARMInstrInfo.td1516 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1523 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1524 iii, opc, "\t$Rd, $Rn, $imm",
1525 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1528 bits<4> Rn;
1531 let Inst{19-16} = Rn;
1536 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1537 iir, opc, "\t$Rd, $Rn, $Rm",
1538 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1541 bits<4> Rn;
[all …]
DARMInstrThumb.td423 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
434 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
455 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
456 "add", "\t$Rdn, $sp, $Rn", []>,
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
826 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
827 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
828 bits<3> Rn;
830 let Inst{10-8} = Rn;
840 "$Rn = $wb", IIC_iLoad_mu>,
[all …]
DARMInstrNEON.td544 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
546 [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))]>;
551 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
553 [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>;
601 (ins AddrMode:$Rn), IIC_VLD1,
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
604 let Inst{4} = Rn{4};
609 (ins AddrMode:$Rn), IIC_VLD1x2,
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
612 let Inst{5-4} = Rn{5-4};
[all …]
DARMInstrCDE.td84 dag Rn;
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
136 bits<4> Rn;
140 let Inst{19-16} = Rn{3-0};
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
154 bits<4> Rn;
159 let Inst{19-16} = Rn{3-0};
170 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
178 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
189 let Iops2 = !con(IOpsPrefix, ops.Rn);
[all …]
DARMInstrFormats.td75 // The instruction has an Rn register operand.
77 // it doesn't have a Rn operand.
800 bits<4> Rn;
803 let Inst{19-16} = Rn;
818 bits<4> Rn;
821 let Inst{19-16} = Rn;
834 // {17-14} Rn
858 let Inst{19-16} = addr{12-9}; // Rn
888 // {12-9} Rn
898 let Inst{19-16} = addr; // Rn
[all …]
DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
20 // | | uopc Rd, Rn, T0 - P01 - 1
23 // and one cycle after the result in Rn is available. The micro-ops can execute
26 // that the resource P01 is needed and that the latency to Rn is different than
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrVFP.td231 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
233 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
239 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
248 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
259 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
261 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
271 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
[all …]
DARMInstrMVE.td361 def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn)))),
362 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn))>;
368 (VTI.Vec (ARMvdup rGPR:$Rn)))),
370 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
377 (ARMvdup rGPR:$Rn),
379 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
385 def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))),
388 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
5711 : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
5713 iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
[all …]
DThumb2SizeReduction.cpp468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
473 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
481 .addReg(Rn, RegState::Define) in ReduceLoadStore()
482 .addReg(Rn) in ReduceLoadStore()
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp2483 Rn; // This function assumes Rn is the SP, but we should verify that. in EmulateSTRRtSP() local
2492 Rn = Bits32(opcode, 19, 16); in EmulateSTRRtSP()
2494 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP. in EmulateSTRRtSP()
2501 if (wback && ((Rn == 15) || (Rn == Rt))) in EmulateSTRRtSP()
2956 uint32_t Rn; // the base register which contains the address of the table of in EmulateTB() local
2963 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2966 if (Rn == 13 || BadReg(Rm)) in EmulateTB()
2977 uint32_t base = ReadCoreReg(Rn, &success); in EmulateTB()
3106 uint64_t Rn = in EmulateADDImmThumb() local
3112 AddWithCarryResult res = AddWithCarry(Rn, imm32, 0); in EmulateADDImmThumb()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1908 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1953 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
1978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeSORegMemOperand()
1998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp989 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
994 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
997 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
1080 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
1108 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1129 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1175 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
1226 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1236 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
1294 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeSignedLdStInstruction()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
934 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue() local
1073 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1254 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
1273 Binary |= Rn << 13; in getLdStSORegOpValue()
1351 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local
1359 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1361 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1369 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/
DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
DEmulateInstructionARM64.cpp629 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm() local
635 const uint32_t n = UInt(Rn); in EmulateADDSUBImm()
709 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP() local
712 integer n = UInt(Rn); in EmulateLDPSTP()
/freebsd-12-stable/contrib/binutils/opcodes/
Darm-dis.c3441 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
3449 func (stream, "[%s", arm_regnames[Rn]); in print_insn_thumb32()
3452 else if (Rn == 15) /* 12-bit negative immediate offset */ in print_insn_thumb32()
3508 if (Rn == 15) in print_insn_thumb32()
3522 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
3525 func (stream, "[%s", arm_regnames[Rn]); in print_insn_thumb32()

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