| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 45 EVT ResultVT; in getExtendedVectorVT() local
46 ResultVT.LLVMTy = in getExtendedVectorVT()
48 assert(ResultVT.isExtended() && "Type is not extended!"); in getExtendedVectorVT()
49 return ResultVT; in getExtendedVectorVT()
53 EVT ResultVT; in getExtendedVectorVT() local
54 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), EC); in getExtendedVectorVT()
55 assert(ResultVT.isExtended() && "Type is not extended!"); in getExtendedVectorVT()
56 return ResultVT; in getExtendedVectorVT()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypes.cpp | 240 EVT ResultVT = N->getValueType(i); in run() local
241 LLVM_DEBUG(dbgs() << "Analyzing result type: " << ResultVT.getEVTString() in run()
243 switch (getTypeAction(ResultVT)) { in run()
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| D | SelectionDAGBuilder.cpp | 6770 EVT ResultVT = Op1.getValueType(); in visitIntrinsicCall() local
6772 if (ResultVT.isVector()) in visitIntrinsicCall()
6774 *Context, OverflowVT, ResultVT.getVectorElementCount()); in visitIntrinsicCall()
6776 SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT); in visitIntrinsicCall()
7171 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntrinsicCall() local
7172 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
7181 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntrinsicCall() local
7190 setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index)); in visitIntrinsicCall()
8837 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType); in visitInlineAsm() local
8849 if (ResultVT != V.getValueType() && in visitInlineAsm()
[all …]
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| D | DAGCombiner.cpp | 18586 EVT ResultVT = EVE->getValueType(0); in scalarizeExtractedVectorLoad() local
18603 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad()
18632 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
18635 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, in scalarizeExtractedVectorLoad()
18639 Load = DAG.getExtLoad(ExtType, SDLoc(EVE), ResultVT, in scalarizeExtractedVectorLoad()
18649 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
18650 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load); in scalarizeExtractedVectorLoad()
18652 Load = DAG.getBitcast(ResultVT, Load); in scalarizeExtractedVectorLoad()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 5539 EVT ResultVT = Op.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5568 if (ResultVT == MVT::f16) { in lowerEXTRACT_VECTOR_ELT()
5570 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result); in lowerEXTRACT_VECTOR_ELT()
5573 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT); in lowerEXTRACT_VECTOR_ELT()
5584 EVT ResultVT = Op.getValueType(); in lowerVECTOR_SHUFFLE() local
5587 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16; in lowerVECTOR_SHUFFLE()
5602 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) { in lowerVECTOR_SHUFFLE()
5630 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
11044 MVT ResultVT = NewChannels == 1 ? in adjustWritemask() local
11048 DAG.getVTList(ResultVT, MVT::Other) : DAG.getVTList(ResultVT); in adjustWritemask()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 225 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2237 EVT ResultVT = EVT::getVectorVT(Context, SrcEltVT, Count); in LowerOperation() local
2238 Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR_VL, DL, ResultVT, Result, in LowerOperation()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5887 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, in extractSubVector() local
5900 return DAG.getBuildVector(ResultVT, dl, in extractSubVector()
5904 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
5937 EVT ResultVT = Result.getValueType(); in insertSubVector() local
5948 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
19716 MVT ResultVT = Op0.getSimpleValueType(); in LowerFunnelShift() local
19720 DAG.getNode(IsFSHR ? X86ISD::VSHRD : X86ISD::VSHLD, DL, ResultVT, Op0, in LowerFunnelShift()
19726 ResultVT, Op0, Op1, Amt); in LowerFunnelShift()
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