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Searched refs:ResourceCycles (Results 1 – 25 of 54) sorted by relevance

123

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86SchedSkylakeClient.td97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
421 let ResourceCycles = [2];
486 let ResourceCycles = [3];
491 let ResourceCycles = [3,1];
498 let ResourceCycles = [4,3,1,1];
503 let ResourceCycles = [4,3,1,1,1];
510 let ResourceCycles = [3];
515 let ResourceCycles = [3,1];
522 let ResourceCycles = [4,3,1];
[all …]
DX86SchedHaswell.td103 let ResourceCycles = Res;
111 let ResourceCycles = !listconcat([1], Res);
473 let ResourceCycles = [2];
496 let ResourceCycles = [3];
501 let ResourceCycles = [3,1];
508 let ResourceCycles = [4,3,1,1];
513 let ResourceCycles = [4,3,1,1,1];
520 let ResourceCycles = [3];
525 let ResourceCycles = [3,1];
532 let ResourceCycles = [4,3,1];
[all …]
DX86SchedSkylakeServer.td97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
422 let ResourceCycles = [2];
487 let ResourceCycles = [3];
492 let ResourceCycles = [3,1];
499 let ResourceCycles = [4,3,1,1];
504 let ResourceCycles = [4,3,1,1,1];
511 let ResourceCycles = [3];
516 let ResourceCycles = [3,1];
523 let ResourceCycles = [4,3,1];
[all …]
DX86SchedBroadwell.td98 let ResourceCycles = Res;
106 let ResourceCycles = !listconcat([1], Res);
431 let ResourceCycles = [2];
495 let ResourceCycles = [3];
500 let ResourceCycles = [3,1];
507 let ResourceCycles = [4,3,1,1];
512 let ResourceCycles = [4,3,1,1,1];
519 let ResourceCycles = [3];
524 let ResourceCycles = [3,1];
531 let ResourceCycles = [4,3,1];
[all …]
DX86ScheduleAtom.td63 let ResourceCycles = RRRes;
69 let ResourceCycles = RMRes;
118 let ResourceCycles = [2];
122 let ResourceCycles = [2];
457 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
458 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
460 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
490 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
491 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
500 let ResourceCycles = [1];
[all …]
DX86SchedSandyBridge.td93 let ResourceCycles = Res;
101 let ResourceCycles = !listconcat([1], Res);
474 let ResourceCycles = [3];
479 let ResourceCycles = [3,1];
485 let ResourceCycles = [8];
489 let ResourceCycles = [7, 1];
496 let ResourceCycles = [3];
501 let ResourceCycles = [3,1];
507 let ResourceCycles = [8];
511 let ResourceCycles = [7, 1];
[all …]
DX86ScheduleBdVer2.td195 let ResourceCycles = Res;
268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
271 def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
277 def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
311 let ResourceCycles = [375];
319 def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
329 let ResourceCycles = [3, 2, 1];
336 let ResourceCycles = [88];
343 let ResourceCycles = [2];
355 let ResourceCycles = [3, 3];
[all …]
DX86ScheduleZnver3.td405 let ResourceCycles = Res;
504 let ResourceCycles = [3, 1];
518 let ResourceCycles = [1, 1, 4];
525 let ResourceCycles = [4, 1, 1];
535 let ResourceCycles = [4];
546 let ResourceCycles = [4];
553 let ResourceCycles = [2];
560 let ResourceCycles = [1];
570 let ResourceCycles = [1, 1, 7, 1];
581 let ResourceCycles = [1];
[all …]
DX86ScheduleBtVer2.td128 let ResourceCycles = Res;
136 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
148 let ResourceCycles = Res;
156 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
168 let ResourceCycles = Res;
176 let ResourceCycles = !listconcat([2], Res);
313 let ResourceCycles = [3];
319 let ResourceCycles = [3,16,16];
325 let ResourceCycles = [3,17,17];
331 let ResourceCycles = [3,1,1];
[all …]
DX86ScheduleZnver1.td139 let ResourceCycles = Res;
147 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
160 let ResourceCycles = Res;
168 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
462 let ResourceCycles = [1, 2];
467 let ResourceCycles = [1, 2, 3];
478 let ResourceCycles = [2];
666 let ResourceCycles = [1, 2];
673 let ResourceCycles = [1, 2, 2];
967 let ResourceCycles = [1,3];
[all …]
DX86ScheduleZnver2.td138 let ResourceCycles = Res;
146 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
159 let ResourceCycles = Res;
167 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
444 let ResourceCycles = [1, 2];
449 let ResourceCycles = [1, 2, 3];
460 let ResourceCycles = [2];
664 let ResourceCycles = [1, 2];
671 let ResourceCycles = [1, 2, 2];
976 let ResourceCycles = [1,3];
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/MCA/
DSupport.cpp23 ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) { in operator +=()
94 unsigned ResourceCycles = ProcResourceUsage[I]; in computeBlockRThroughput() local
95 if (!ResourceCycles) in computeBlockRThroughput()
99 double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits; in computeBlockRThroughput()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/
DSupport.h51 class ResourceCycles {
55 ResourceCycles() : Numerator(0), Denominator(1) {} in ResourceCycles() function
56 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
70 ResourceCycles &operator+=(const ResourceCycles &RHS);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td231 let ResourceCycles = [8];
236 let ResourceCycles = [8];
241 let ResourceCycles = [8];
265 let ResourceCycles = [5];
270 let ResourceCycles = [8];
275 let ResourceCycles = [8];
280 let ResourceCycles = [5];
285 let ResourceCycles = [10];
290 let ResourceCycles = [10];
295 let ResourceCycles = [8];
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMScheduleA57WriteRes.td31 let ResourceCycles = [17]; }
33 let ResourceCycles = [18]; }
35 let ResourceCycles = [19]; }
37 let ResourceCycles = [20]; }
40 let ResourceCycles = [1]; }
42 let ResourceCycles = [1]; }
48 let ResourceCycles = [1]; }
50 let ResourceCycles = [32]; }
52 let ResourceCycles = [32]; }
54 let ResourceCycles = [35]; }
[all …]
DARMScheduleR52.td75 let Latency = 8; let ResourceCycles = [8]; // non-pipelined
110 let ResourceCycles = [7]; // is not pipelined
115 let ResourceCycles = [17];
148 let Latency = 8; let ResourceCycles = [8]; // not pipelined
555 let ResourceCycles = [Num];
642 let ResourceCycles = [1];
647 let ResourceCycles = [2];
652 let ResourceCycles = [3];
657 let ResourceCycles = [4];
662 let ResourceCycles = [5];
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedA55.td76 let Latency = 8; let ResourceCycles = [8];
79 let Latency = 8; let ResourceCycles = [8];
91 let ResourceCycles = [3]; }
95 let ResourceCycles = [2]; }
97 let ResourceCycles = [3]; }
99 let ResourceCycles = [4]; }
101 let ResourceCycles = [5]; }
103 let ResourceCycles = [6]; }
105 let ResourceCycles = [7]; }
107 let ResourceCycles = [8]; }
[all …]
DAArch64SchedThunderX.td61 let ResourceCycles = [1];
66 let ResourceCycles = [1];
72 let ResourceCycles = [6];
77 let ResourceCycles = [8];
88 let ResourceCycles = [3];
93 let ResourceCycles = [1];
98 let ResourceCycles = [7];
103 let ResourceCycles = [8];
108 let ResourceCycles = [9];
113 let ResourceCycles = [9];
[all …]
DAArch64SchedExynosM3.td117 let ResourceCycles = [2]; }
209 let ResourceCycles = [1, 12]; }
212 let ResourceCycles = [1, 21]; }
215 let ResourceCycles = [2]; }
240 let ResourceCycles = [12]; }
302 let ResourceCycles = [8, 8]; }
306 let ResourceCycles = [13, 13]; }
310 let ResourceCycles = [19, 19]; }
314 let ResourceCycles = [26, 26]; }
325 let ResourceCycles = [8]; }
[all …]
DAArch64SchedExynosM4.td144 let ResourceCycles = [2]; }
178 let ResourceCycles = [2]; }
181 let ResourceCycles = [12]; }
183 let ResourceCycles = [21]; }
267 let ResourceCycles = [6, 6]; }
270 let ResourceCycles = [6, 6]; }
273 let ResourceCycles = [9, 9]; }
276 let ResourceCycles = [7, 7]; }
279 let ResourceCycles = [6, 6]; }
282 let ResourceCycles = [9, 9]; }
[all …]
DAArch64SchedA53.td85 let ResourceCycles = [3]; }
88 let ResourceCycles = [2]; }
90 let ResourceCycles = [3]; }
92 let ResourceCycles = [4]; }
94 let ResourceCycles = [5]; }
108 let ResourceCycles = [2];}
111 let ResourceCycles = [2]; }
113 let ResourceCycles = [3]; }
135 let ResourceCycles = [29]; }
138 let ResourceCycles = [14]; }
[all …]
DAArch64SchedExynosM5.td144 let ResourceCycles = [2]; }
146 let ResourceCycles = [2]; }
196 let ResourceCycles = [2]; }
199 let ResourceCycles = [10]; }
201 let ResourceCycles = [16]; }
230 let ResourceCycles = [1, 1, 1, 1, 15]; }
237 let ResourceCycles = [1, 1, 1, 1, 15]; }
241 let ResourceCycles = [1, 13]; }
245 let ResourceCycles = [1, 13]; }
284 let ResourceCycles = [7, 7]; }
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVSchedSiFive7.td63 let ResourceCycles = [1, 15];
67 let ResourceCycles = [1, 15];
114 let ResourceCycles = [1, 26]; }
116 let ResourceCycles = [1, 26]; }
130 let ResourceCycles = [1, 55]; }
132 let ResourceCycles = [1, 55]; }
DRISCVSchedRocket.td70 let ResourceCycles = [34];
74 let ResourceCycles = [33];
158 let Latency = 20, ResourceCycles = [20] in {
165 let ResourceCycles = [20]; }
167 let ResourceCycles = [25]; }
/freebsd-12-stable/contrib/llvm-project/llvm/lib/MCA/Stages/
DInstructionTables.cpp41 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits))); in execute()
56 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits))); in execute()

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