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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5653 string kind2, RegisterOperand RegType,
5656 BaseSIMDThreeSameVectorTied<Q, U, 0b100, {0b1001, Mixed}, RegType, asm, kind1,
5657 [(set (AccumType RegType:$dst),
5658 (OpNode (AccumType RegType:$Rd),
5659 (InputType RegType:$Rn),
5660 (InputType RegType:$Rm)))]> {
5675 string kind2, RegisterOperand RegType,
5678 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5679 [(set (AccumType RegType:$dst),
5680 (OpNode (AccumType RegType:$Rd),
[all …]
DAArch64FrameLowering.cpp2223 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
DAArch64InstrInfo.td900 string rhs_kind, RegisterOperand RegType,
903 lhs_kind, rhs_kind, RegType, AccumType,
905 let Pattern = [(set (AccumType RegType:$dst),
906 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
910 (InputType RegType:$Rn))))];
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DCodeGenPrepare.cpp7000 MVT RegType = TLI->getRegisterType(Context, OldVT); in optimizeSwitchInst() local
7001 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
7020 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchInst()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTarget.td223 // RegType - Specify the list ValueType of the registers in this register