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Searched refs:Reg1 (Results 1 – 25 of 42) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp625 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
650 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
669 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp760 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
763 .addImm(Reg1) in InsertSEH()
773 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
774 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
781 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
811 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
814 .addImm(Reg1) in InsertSEH()
822 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
823 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
830 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
[all …]
DAArch64LowerHomogeneousPrologEpilog.cpp199 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
201 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitStore()
213 .addReg(Reg1) in emitStore()
222 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
224 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitLoad()
236 .addReg(Reg1, getDefRegState(true)) in emitLoad()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp417 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
1028 if (parseRegister(Reg1)) in parseAddress()
1047 if (parseIntegerRegister(Reg1, RegGroup)) in parseAddress()
1101 Register Reg1, Reg2; in parseAddress() local
1108 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1123 if (parseAddressRegister(Reg1)) in parseAddress()
1125 Base = Regs[Reg1.Num]; in parseAddress()
1136 if (parseAddressRegister(Reg1)) in parseAddress()
1141 Index = Regs[Reg1.Num]; in parseAddress()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsTargetStreamer.h130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsAsmPrinter.cpp875 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
884 unsigned Temp = Reg1; in EmitInstrRegReg()
885 Reg1 = Reg2; in EmitInstrRegReg()
889 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
895 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
899 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
906 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
910 unsigned temp = Reg1; in EmitMovFPIntPair()
911 Reg1 = Reg2; in EmitMovFPIntPair()
914 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
292 MIB3.addReg(Reg1); in adjustStackPtrBig()
296 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
387 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
DMipsSEFrameLowering.cpp465 unsigned Reg1 = in emitPrologue() local
469 std::swap(Reg0, Reg1); in emitPrologue()
477 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
485 std::swap(Reg0, Reg1); in emitPrologue()
493 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
214 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
220 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
226 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
232 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
239 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
242 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
[all …]
DMipsMCCodeEmitter.cpp99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch() local
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
104 if (Reg0 < Reg1) in LowerCompactBranch()
107 if (Reg0 >= Reg1) in LowerCompactBranch()
111 if (Reg1 >= Reg0) in LowerCompactBranch()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/
DMCRegisterInfo.h78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
79 return contains(Reg1) && contains(Reg2); in contains()
748 uint16_t Reg1 = 0; variable
756 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
772 Reg0 = Reg1;
773 Reg1 = 0;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrBuilder.h165 unsigned Reg1, bool isKill1, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
DX86ExpandPseudo.cpp468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in ExpandMI() local
473 .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
502 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in ExpandMI() local
515 MIBHi.addReg(Reg1, getKillRegState(SrcIsKill)); in ExpandMI()
DX86AvoidStoreForwardingBlocks.cpp396 Register Reg1 = MRI->createVirtualRegister( in buildCopy() local
400 Reg1) in buildCopy()
425 .addReg(Reg1) in buildCopy()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
264 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTargetInstrInfo.cpp185 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteInstructionImpl() local
198 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1) in commuteInstructionImpl()
206 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
214 Reg0 = Reg1; in commuteInstructionImpl()
231 CommutedMI->getOperand(Idx2).setReg(Reg1); in commuteInstructionImpl()
243 if (Register::isPhysicalRegister(Reg1)) in commuteInstructionImpl()
DAggressiveAntiDepBreaker.h105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h100 bool contains(Register Reg1, Register Reg2) const { in contains() argument
103 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
105 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp1437 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1441 printRegName(O, Reg1); in printVectorListTwo()
1450 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1454 printRegName(O, Reg1); in printVectorListTwoSpaced()
1505 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1509 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1552 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1556 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp82 const DebugLoc &DL, unsigned Reg1,
448 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
454 .addReg(Reg1) in createRegSequence()
DThumb2SizeReduction.cpp757 Register Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
768 if (Reg1 != Reg0) in ReduceTo2Addr()
775 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp877 Register Reg1 = Reg; in lowerCRSpilling() local
882 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
922 Register Reg1 = Reg; in lowerCRRestore() local
928 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
1036 Register Reg1 = Reg; in lowerCRBitSpilling() local
1041 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()

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