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Searched refs:RISCVTargetLowering (Results 1 – 8 of 8) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelDAGToDAG.cpp242 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
268 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG()
283 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF()
311 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF()
327 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG()
346 RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVLXSEG()
359 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG()
378 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG()
408 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG()
423 RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVSXSEG()
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DRISCVCallLowering.h23 class RISCVTargetLowering; variable
28 RISCVCallLowering(const RISCVTargetLowering &TLI);
DRISCVISelLowering.cpp45 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, in RISCVTargetLowering() function in RISCVTargetLowering
873 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType()
884 MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const { in getVPExplicitVectorLengthTy()
888 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, in getTgtMemIntrinsic()
917 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode()
943 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const { in isLegalICmpImmediate()
947 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { in isLegalAddImmediate()
954 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { in isTruncateFree()
962 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree()
971 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
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DRISCVSubtarget.h71 RISCVTargetLowering TLInfo;
98 const RISCVTargetLowering *getTargetLowering() const override { in getTargetLowering()
DRISCVTargetTransformInfo.h34 const RISCVTargetLowering *TLI;
37 const RISCVTargetLowering *getTLI() const { return TLI; } in getTLI()
DRISCVCallLowering.cpp21 RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI) in RISCVCallLowering()
DRISCVISelLowering.h288 class RISCVTargetLowering : public TargetLowering {
292 explicit RISCVTargetLowering(const TargetMachine &TM,
511 const RISCVTargetLowering &TLI,
DRISCVInstrInfoA.td135 // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
321 // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.