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Searched refs:RB (Results 1 – 25 of 58) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td19 bits<5> RB;
25 let Inst{16-20} = RB;
32 let RB = 0;
46 bits<5> RB;
51 let Inst{16-20} = RB;
60 bits<5> RB;
66 let Inst{16-20} = RB;
73 let RB = 0;
87 bits<5> RB;
94 let Inst{16-20} = RB;
[all …]
DPPCExpandAtomicPseudoInsts.cpp147 Register RB = MI.getOperand(3).getReg(); in expandAtomicRMW128() local
153 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
195 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
224 Register RB = MI.getOperand(3).getReg(); in expandAtomicCmpSwap128() local
257 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
277 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
286 BuildMI(CurrentMBB, DL, SC).addReg(Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
DPPCInstrHTM.td106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
DPPCInstrFormats.td564 bits<5> RB;
570 let Inst{16-20} = RB;
580 bits<5> RB;
585 let Inst{16-20} = RB;
614 bits<5> RB;
617 let Inst{16-20} = RB;
741 // [PO RT /// RB XO RC]
945 // [PO RT RA RB XO /]
952 bits<5> RB;
960 let Inst{16-20} = RB;
[all …]
DPPCInstr64Bit.td929 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
930 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
932 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
933 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
934 def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
935 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
936 … [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>,
940 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
941 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
942 … [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
[all …]
/freebsd-12-stable/contrib/binutils/opcodes/
Dppc-opc.c380 #define RB RAOPT + 1 macro
387 #define RBS RB + 1
1716 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1717 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1718 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1719 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1720 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1721 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1722 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1723 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
[all …]
/freebsd-12-stable/contrib/llvm-project/clang/lib/Rewrite/
DHTMLRewrite.cpp58 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E, in HighlightRange() argument
62 RB.InsertTextAfter(B, StartTag); in HighlightRange()
63 RB.InsertTextBefore(E, EndTag); in HighlightRange()
77 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag); in HighlightRange()
96 RB.InsertTextAfter(i, StartTag); in HighlightRange()
116 RewriteBuffer &RB = R.getEditBuffer(FID); in EscapeText() local
129 RB.ReplaceText(FilePos, 1, "&nbsp;"); in EscapeText()
133 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText()
142 RB.ReplaceText(FilePos, 1, in EscapeText()
146 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces)); in EscapeText()
[all …]
DRewriter.cpp162 const RewriteBuffer &RB = I->second; in getRangeSize() local
163 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange); in getRangeSize()
164 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange); in getRangeSize()
213 const RewriteBuffer &RB = I->second; in getRewrittenText() local
214 EndOff = RB.getMappedOffset(EndOff, true); in getRewrittenText()
215 StartOff = RB.getMappedOffset(StartOff); in getRewrittenText()
223 RewriteBuffer::iterator Start = RB.begin(); in getRewrittenText()
398 RewriteBuffer &RB = getEditBuffer(FID); in IncreaseIndentation() local
406 RB.InsertText(offs, indent, /*InsertAfter=*/false); in IncreaseIndentation()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DRDFRegisters.h118 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
120 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
121 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
163 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
182 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
184 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
/freebsd-12-stable/contrib/llvm-project/clang/lib/Frontend/Rewrite/
DRewriteMacros.cpp94 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local
133 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
139 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
169 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); in RewriteMacrosInInput()
187 RB.InsertTextBefore(EndPos, "*/"); in RewriteMacrosInInput()
203 RB.InsertTextBefore(InsertPos, Expansion); in RewriteMacrosInInput()
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
Dsanitizer_ring_buffer.h27 RingBuffer *RB = reinterpret_cast<RingBuffer*>(Ptr); in New() local
29 RB->last_ = RB->next_ = reinterpret_cast<T*>(End - sizeof(T)); in New()
30 return RB; in New()
/freebsd-12-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
DMacOSXAPIChecker.cpp77 const MemRegion *RB = R->getBaseRegion(); in CheckDispatchOnce() local
78 const MemSpaceRegion *RS = RB->getMemorySpace(); in CheckDispatchOnce()
96 if (const VarRegion *VR = dyn_cast<VarRegion>(RB)) { in CheckDispatchOnce()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCSEInfo.cpp347 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { in addNodeIDRegType()
348 ID.AddPointer(RB); in addNodeIDRegType()
390 if (const auto *RB = RCOrRB.dyn_cast<const RegisterBank *>()) in addNodeIDReg() local
391 addNodeIDRegType(RB); in addNodeIDReg()
DRegisterBankInfo.cpp93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() local
94 return RB; in getRegBank()
140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() local
142 if (RB && !RB->covers(RC)) in constrainGenericRegister()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
396 const RegisterBank &RB, in getLoadStoreOp() argument
405 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
408 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
411 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
413 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DRDFRegisters.cpp136 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { in aliasRR()
138 assert(Register::isPhysicalRegister(RB.Reg)); in aliasRR()
141 MCRegUnitMaskIterator UMB(RB.Reg, &TRI); in aliasRR()
152 if (PB.second.any() && (PB.second & RB.Mask).none()) { in aliasRR()
/freebsd-12-stable/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/lua/
Dlvm.c551 #define RB(i) check_exp(getBMode(GET_OPCODE(i)) == OpArgR, base+GETARG_B(i)) macro
618 setobjs2s(L, ra, RB(i)); in luaV_execute()
649 Protect(luaV_gettable(L, RB(i), RKC(i), ra)); in luaV_execute()
673 StkId rb = RB(i); in luaV_execute()
699 TValue *rb = RB(i); in luaV_execute()
709 TValue *rb = RB(i); in luaV_execute()
714 Protect(luaV_objlen(L, ra, RB(i))); in luaV_execute()
764 TValue *rb = RB(i); in luaV_execute()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp151 const RegisterBank &RB,
483 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() argument
486 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
498 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
516 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits, in getMinClassForRegBank() argument
518 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
580 static unsigned getMinSizeForRegBank(const RegisterBank &RB) { in getMinSizeForRegBank() argument
581 switch (RB.getID()) { in getMinSizeForRegBank()
2306 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local
2307 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
[all …]
DAArch64RegisterBankInfo.cpp98 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \ in AArch64RegisterBankInfo() argument
101 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \ in AArch64RegisterBankInfo()
505 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
506 if (RB == &AArch64::FPRRegBank) in hasFPConstraints()
508 if (RB == &AArch64::GPRRegBank) in hasFPConstraints()
DAArch64RegisterBankInfo.h65 unsigned ValLength, const RegisterBank &RB);
/freebsd-12-stable/contrib/lua/src/
Dlvm.c729 #define RB(i) check_exp(getBMode(GET_OPCODE(i)) == OpArgR, base+GETARG_B(i)) macro
804 setobjs2s(L, ra, RB(i)); in luaV_execute()
843 StkId rb = RB(i); in luaV_execute()
879 StkId rb = RB(i); in luaV_execute()
1032 TValue *rb = RB(i); in luaV_execute()
1047 TValue *rb = RB(i); in luaV_execute()
1058 TValue *rb = RB(i); in luaV_execute()
1064 Protect(luaV_objlen(L, ra, RB(i))); in luaV_execute()
1121 TValue *rb = RB(i); in luaV_execute()
/freebsd-12-stable/contrib/llvm-project/clang/include/clang/Rewrite/Core/
DHTMLRewrite.h47 void HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
/freebsd-12-stable/contrib/llvm-project/clang/lib/Frontend/
DPrecompiledPreamble.cpp543 for (const auto &RB : PreprocessorOpts.RemappedFileBuffers) { in CanReuse() local
545 PreambleFileHash::createForMemoryBuffer(RB.second->getMemBufferRef()); in CanReuse()
547 if (moveOnNoError(VFS.status(RB.first), Status)) in CanReuse()
550 OverridenFileBuffers[RB.first] = PreambleHash; in CanReuse()
552 llvm::SmallString<128> MappedPath(RB.first); in CanReuse()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp255 MachineBasicBlock::iterator RB = Begin; in runOnMachineFunction() local
256 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF)) in runOnMachineFunction()
257 ++RB; in runOnMachineFunction()
260 MachineBasicBlock::iterator RE = RB; in runOnMachineFunction()
267 if (RB != End) in runOnMachineFunction()
268 Packetizer.PacketizeMIs(&MB, RB, RE); in runOnMachineFunction()
DHexagonGenInsert.cpp236 BitValueOrdering(const RegisterOrdering &RB) : BaseOrd(RB) {} in BitValueOrdering()
530 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
627 void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB, in buildOrderingBT() argument
631 BitValueOrdering BVO(RB); in buildOrderingBT()
637 for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I) in buildOrderingBT()

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