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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrSNP.td19 let Uses = [RAX] in
24 let Uses = [RAX] in
33 let Uses = [RAX] in
38 let Uses = [RAX] in
DX86InstrSVM.td35 let Uses = [RAX] in
43 let Uses = [RAX] in
51 let Uses = [RAX] in
59 let Uses = [RAX, ECX] in
DX86InstrArithmetic.td77 // RAX,RDX = RAX*GR64
78 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
81 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>,
101 // RAX,RDX = RAX*[mem64]
102 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
121 // RAX,RDX = RAX*GR64
122 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
139 // RAX,RDX = RAX*[mem64]
140 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
292 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86CallingConv.td44 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
349 // The X86-Win64 calling convention always returns __m64 values in RAX.
352 // GCC returns FP values in RAX on Win64.
376 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
384 // Return: RAX
385 CCIfType<[i64], CCAssignToReg<[RAX]>>
398 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
[all …]
DX86WinAllocaExpander.cpp220 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
234 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
248 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower()
DX86InstrExtension.td20 let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
32 let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
431 let Defs = [RAX, RDX], Uses = [ECX] in
585 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
599 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
603 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
682 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
744 // "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
746 // indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
750 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
DX86RegisterBanks.td12 /// General Purpose Registers: RAX, RCX,...
DX86RegisterInfo.td169 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
436 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
460 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
462 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
464 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
484 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
523 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
DX86MCInstLower.cpp330 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
357 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
391 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
788 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; in Lower()
1114 BaseReg = X86::RAX; in emitNop()
1141 IndexReg = X86::RAX; in emitNop()
1147 IndexReg = X86::RAX; in emitNop()
1158 IndexReg = X86::RAX; in emitNop()
1164 IndexReg = X86::RAX; in emitNop()
1170 IndexReg = X86::RAX; in emitNop()
[all …]
DX86LowerTileCopy.cpp102 Register GR64Cand = X86::RAX; in runOnMachineFunction()
DX86SelectionDAGInfo.cpp57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
123 ValReg = X86::RAX; in EmitTargetCodeForMemset()
DX86FrameLowering.cpp156 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || in isEAXLiveIn()
233 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX); in emitSPUpdate()
294 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
800 const Register SizeReg = InProlog ? X86::RAX in emitStackProbeInlineWindowsCoreCLR64()
857 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX); in emitStackProbeInlineWindowsCoreCLR64()
1010 unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX; in emitStackProbeCall()
1652 .addReg(X86::RAX, RegState::Kill) in emitPrologue()
1671 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX) in emitPrologue()
1675 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) in emitPrologue()
1694 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX), in emitPrologue()
[all …]
DX86ExpandPseudo.cpp219 TRI->regsOverlap(Op.getReg(), X86::RAX)) { in expandCALL_RVMARKER()
233 .addReg(X86::RAX) in expandCALL_RVMARKER()
253 .addReg(X86::RAX, in expandCALL_RVMARKER()
DX86InstrInfo.td1561 let Defs = [RDI], Uses = [RAX,RDI,DF] in
1575 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in
1688 let Defs = [RAX] in
1717 let Uses = [RAX] in
1750 let Defs = [RAX] in
1769 let Uses = [RAX] in
2148 let Uses = [RAX], Defs = [RAX] in
2202 let Defs = [RAX, EFLAGS], Uses = [RAX] in
2222 let Defs = [RAX, EFLAGS], Uses = [RAX] in
2231 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
[all …]
DX86InstrCompiler.td117 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
134 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
161 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
409 let Uses = [RAX,RCX,RDI] in
427 let Uses = [RAX,RCX,RDI] in
433 let Uses = [RAX,RCX,RDI] in
469 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
511 let Defs = [RAX, EFLAGS, DF],
844 let Defs = [RAX, EFLAGS], Uses = [RAX] in
859 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
[all …]
DX86InstructionSelector.cpp1552 X86::RAX, in selectDivRem()
1555 {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv in selectDivRem()
1557 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv in selectDivRem()
DX86SchedHaswell.td1934 // Unfortunately, this optimization does not apply to the AX/EAX/RAX short
1935 // encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since
1943 CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX
DX86FastISel.cpp1294 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet()
1919 { &X86::GR64RegClass, X86::RAX, X86::RDX, { in X86SelectDivRem()
1920 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv in X86SelectDivRem()
1922 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv in X86SelectDivRem()
2935 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; in fastLowerIntrinsicCall()
DX86ISelDAGToDAG.cpp4680 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select()
4989 LoReg = X86::RAX; in Select()
5072 LoReg = UseMULX ? X86::RDX : X86::RAX; in Select()
5206 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
DX86ScheduleBtVer2.td374 // including the implicit read of RAX.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp154 {codeview::RegisterId::RAX, X86::RAX}, in initLLVMToSEHAndCVRegMapping()
627 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
639 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
676 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
712 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
748 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
749 return X86::RAX; in getX86SubSuperRegisterOrZero()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h170 ENTRY(RAX) \
188 ENTRY(RAX) \
/freebsd-12-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h42 #define RAX 0 macro
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def220 CV_REGISTER(RAX, 328)

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