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Searched refs:R7 (Results 1 – 25 of 66) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
Dfastmath_dlib_asm.S65 #define mantexpd R7:6
72 #define zero R7:6
200 #define mantexpd R7:6
207 #define zero R7:6
329 #define mantexpd R7:6
334 #define zero0 R7:6
Dfastmath2_dlib_asm.S63 #define mantexpd R7:6
164 #define mantexpd R7:6
266 #define mantexpd R7:6
267 #define mantdh R7
378 #define c07f R7
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp42 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
DMSP430RegisterInfo.td62 def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
DXCoreRegisterInfo.cpp214 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
DPPCCallingConv.td78 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
89 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
187 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
202 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
286 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
288 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
304 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
309 // Also save R7-R4 first to match the stack frame fixed spill areas.
310 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
318 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
331 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
DThumb1FrameLowering.cpp224 case ARM::R7: in emitPrologue()
289 case ARM::R7: in emitPrologue()
684 if (STI.getFramePointerReg() == ARM::R7) in emitPopSpecialFixUp()
685 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
983 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
DARMSLSHardening.cpp141 {"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
155 {"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
DARMSubtarget.h825 return ARM::R7; in getFramePointerReg()
834 return (getFramePointerReg() == ARM::R7 && in splitFramePushPop()
DARMBaseRegisterInfo.h51 case R4: case R5: case R6: case R7: in isARMArea1Register()
DARMRegisterInfo.td84 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
336 // Thumb registers are R0-R7 normally. Some instructions can still use
342 // Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow
362 def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {
519 (add R1, R3, R5, R7, R9, R11)]>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiCallingConv.td24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
DLanaiRegisterInfo.td48 R6, R7, R18, R19, // registers for passing arguments
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
DARCCallingConv.td32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFFrameLowering.cpp36 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td51 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
102 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
132 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/freebsd-12-stable/contrib/gdb/gdb/
Ddpx2-nat.c39 R0, R1, R2, R3, R4, R5, R6, R7,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h59 case Lanai::R7: in getLanaiRegisterNumbering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
DBPFDisassembler.cpp98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};

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