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Searched refs:R4 (Results 1 – 25 of 109) sorted by relevance

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/freebsd-12-stable/contrib/ldns/
Dsha1.c42 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
86 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in ldns_sha1_transform()
87 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in ldns_sha1_transform()
88 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in ldns_sha1_transform()
89 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in ldns_sha1_transform()
90 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in ldns_sha1_transform()
/freebsd-12-stable/contrib/wpa/src/crypto/
Dsha1-internal.c155 #define R4(v,w,x,y,z,i) \ macro
213 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
214 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
215 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
216 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
217 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/freebsd-12-stable/crypto/openssh/openbsd-compat/
Dsha1.c46 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
88 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
89 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
90 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
91 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
92 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/freebsd-12-stable/crypto/openssl/crypto/poly1305/asm/
Dpoly1305-armv4.pl448 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
489 vdup.32 $R4,r6
506 vmull.u32 $D4,$R4,${R0}[1]
508 vmlal.u32 $D0,$R4,${S1}[1]
515 vmlal.u32 $D1,$R4,${S2}[1]
523 vmlal.u32 $D2,$R4,${S3}[1]
526 vmlal.u32 $D3,$R4,${S4}[1]
530 vmlal.u32 $D4,$R0,${R4}[1]
623 vtrn.32 $R4,$D4#lo
628 vshl.u32 $S4,$R4,#2
[all …]
Dpoly1305-armv8.pl214 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
500 ld1 {$S2,$R3,$S3,$R4},[x15],#64
556 umull $ACC4,$IN23_0,${R4}[2]
638 umlal $ACC4,$IN01_0,${R4}[0]
753 umlal2 $ACC4,$IN23_0,${R4}
791 umlal $ACC4,$IN01_0,${R4}
/freebsd-12-stable/contrib/ntp/libntp/lib/isc/
Dsha1.c119 #define R4(v,w,x,y,z,i) \ macro
144 #define nR4(v,w,x,y,z,i) R4(*v,*w,*x,*y,*z,i)
243 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in transform()
244 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in transform()
245 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in transform()
246 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in transform()
247 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in transform()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp42 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
90 Reserved.set(MSP430::R4); in getReservedRegs()
115 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP); in eliminateFrameIndex()
159 return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP; in getFrameRegister()
DMSP430FrameLowering.cpp67 .addReg(MSP430::R4, RegState::Kill); in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
76 I->addLiveIn(MSP430::R4); in emitPrologue()
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4); in emitEpilogue()
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4); in emitEpilogue()
DMSP430RegisterInfo.td59 def R4 : MSP430RegWithSubregs<4, "r4", [R4B], ["fp"]>;
85 R4,
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
Dfastmath2_dlib_asm.S61 #define expa R4
72 #define k R4
162 #define expa R4
173 #define k R4
263 #define expa R4
375 #define expo R4
461 #define maxnegl R4
Dfastmath2_ldlib_asm.S56 #define expa R4
62 #define k R4
155 #define expa R4
161 #define k R4
260 #define expa R4
Dfastmath_dlib_asm.S63 #define expa R4
79 #define k R4
198 #define expa R4
214 #define k R4
327 #define expa R4
339 #define k R4
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMFrameLowering.cpp544 case ARM::R4: in emitPrologue()
646 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
651 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
664 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
675 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
682 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
764 case ARM::R4: in emitPrologue()
858 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
861 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
864 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
[all …]
DThumb1FrameLowering.cpp221 case ARM::R4: in emitPrologue()
286 case ARM::R4: in emitPrologue()
414 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
418 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4) in emitPrologue()
420 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
424 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4) in emitPrologue()
426 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
431 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
517 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
519 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
[all …]
DARMCallingConv.td121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
276 R6, R5, R4, (sequence "D%u", 15, 0))>;
288 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
305 R5, R4, (sequence "D%u", 15, 8),
309 // Also save R7-R4 first to match the stack frame fixed spill areas.
310 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
318 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
331 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
144 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFCallingConv.td22 CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,
38 [R1, R2, R3, R4, R5]>>,
41 CCIfType<[i64], CCAssignToRegWithShadow<[R1, R2, R3, R4, R5],
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td32 def SP : LanaiReg< 4, "sp", [R4]>, DwarfRegAlias<R4>;
53 R4, SP, // stack pointer
/freebsd-12-stable/secure/caroot/trusted/
DGlobalSign_ECC_Root_CA_-_R4.pem2 ## GlobalSign ECC Root CA - R4
21 Issuer: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
25 Subject: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
DGTS_Root_R4.pem2 ## GTS Root R4
21 Issuer: C = US, O = Google Trust Services LLC, CN = GTS Root R4
25 Subject: C = US, O = Google Trust Services LLC, CN = GTS Root R4
/freebsd-12-stable/contrib/gdb/gdb/
Drs6000-tdep.c2146 #define R4(name) { STR(name), 4, 4, 0, 0 } macro
2199 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
2203 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2214 /* 87 */ R4(pvr), \
2219 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2222 /* 116 */ R4(dec), R(dabr), R4(ear)
2230 /*151*/R4(vscr), R4(vrsave)
2251 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2252 /* 71 */ R4(fpscr)
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMathExtras.h295 #define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
296 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
299 #undef R4
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td33 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/freebsd-12-stable/contrib/file/magic/Magdir/
Dpkgadd4 # pkgadd: file(1) magic for SysV R4 PKG Datastreams

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