| /freebsd-12-stable/contrib/gdb/gdb/ |
| D | rs6000-tdep.c | 2154 #define R16(name) { STR(name), 16, 16, 0, 0 } macro
2226 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2227 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2228 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2229 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 60 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
97 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
113 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
149 R28, R29, R17, R16
155 add R23, R22, R21, R20, R19, R18, R17, R16
|
| D | AVRISelLowering.cpp | 1003 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 48 def R16 : Core<16, "%r16">, DwarfRegNum<[16]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 81 case Lanai::R16: in getLanaiRegisterNumbering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 46 (add R3, R9, R12, R13, R14, R16, R17,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 121 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
130 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
|
| D | HexagonFrameLowering.h | 93 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
|
| D | HexagonRegisterInfo.td | 120 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
378 (add R23, R22, R21, R20, R19, R18, R17, R16,
448 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
|
| D | HexagonPseudo.td | 177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
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| D | HexagonFrameLowering.cpp | 1076 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, in insertCFIInstructionsAt()
|
| D | HexagonInstrInfo.cpp | 129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
|
| D | HexagonISelLowering.cpp | 288 .Case("r16", Hexagon::R16) in getRegisterByName()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| D | AVRDisassembler.cpp | 65 AVR::R16, AVR::R17, AVR::R18, AVR::R19,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
|
| D | PPCFrameLowering.cpp | 134 {PPC::R16, -64}, \ in getCalleeSavedSpillSlots()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| D | ARCDisassembler.cpp | 119 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
|
| /freebsd-12-stable/sys/gnu/dts/arm/ |
| D | sun8i-r16-parrot.dts | 53 model = "Allwinner R16 EVB (Parrot)";
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 551 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
566 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeGeneralSubRegsRegisterClass()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| D | CSKYRegisterInfo.td | 68 def R16 : CSKYReg<16, "r16", ["l8"]>, DwarfRegNum<[16]>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 284 case R16: in getDuplexRegisterNumbering()
651 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); in isIntRegForSubInst()
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| D | HexagonMCChecker.cpp | 705 Register = Hexagon::R16; in compoundRegisterMap()
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| D | HexagonMCDuplexInfo.cpp | 680 case Hexagon::R16: in addOps()
|
| /freebsd-12-stable/contrib/gcc/ |
| D | FSFChangeLog.10 | 9871 (FUNCTION_VALUE): R16 is return reg only if !-msoft-float.
|