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Searched refs:R15 (Results 1 – 25 of 49) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td37 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
49 R15, RCA, // register for constant addresses
DLanaiRegisterInfo.cpp58 Reserved.set(Lanai::R15); in getReservedRegs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td45 def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
DARCFrameLowering.cpp165 .addExternalSymbol(store_funclet_name[Last - ARC::R15]) in emitPrologue()
295 .addExternalSymbol(load_funclet_name[Last - ARC::R15]) in emitEpilogue()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
DMSP430RegisterInfo.td70 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td59 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
98 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
113 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
174 // Lower 16-bit pair registers in R0..R15, only used in inline assembly.
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
Dfastmath2_ldlib_asm.S254 #define mantxh R15
255 #define mantx R15:14
Dfastmath2_dlib_asm.S274 #define min R15:14
275 #define minh R15
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h78 case Lanai::R15: in getLanaiRegisterNumbering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp169 {codeview::RegisterId::R15, X86::R15}, in initLLVMToSEHAndCVRegMapping()
669 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
706 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
742 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
778 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
779 return X86::R15; in getX86SubSuperRegisterOrZero()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
376 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
428 RAX, R10, R11, R13, R14, R15]>>
597 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
698 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
719 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
1095 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1103 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1134 R11, R12, R13, R14, R15, RBP,
[all …]
DX86RegisterInfo.td187 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
392 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
437 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
395 let Defs = [R14, R15, R28] in
398 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
401 let Defs = [R14, R15, R28, P0] in
404 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
DHexagonRegisterInfo.cpp72 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
DCSKYMCTargetDesc.cpp63 InitCSKYMCRegisterInfo(Info, CSKY::R15); in createCSKYMCRegisterInfo()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrInfo.td331 let isCall = 1, Defs = [ R15 ] in
334 let isCall = 1, Defs = [ R15 ] , mayLoad = 1 in
347 let Defs = [ R15 ];
DCSKYRegisterInfo.td67 def R15 : CSKYReg<15, "r15", ["lr"]>, DwarfRegNum<[15]>;
150 (sequence "R%u", 18, 25), R15, (sequence "R%u", 4, 11),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h185 ENTRY(R15)
203 ENTRY(R15)
/freebsd-12-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h57 #define R15 7 macro
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp88 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
DAVRDisassembler.cpp64 AVR::R12, AVR::R13, AVR::R14, AVR::R15,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.td271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
DARCDisassembler.cpp119 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,

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