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Searched refs:R14 (Results 1 – 25 of 45) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td44 def R14 : Core<14, "%r14">, DwarfRegNum<[14]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
DARCFrameLowering.cpp155 if (UseSaveRestoreFunclet && Last > ARC::R14) { in emitPrologue()
268 if (UseSaveRestoreFunclet && Last > ARC::R14) { in emitEpilogue()
362 if (MFI.hasCalls() || (UseSaveRestoreFunclet && Last > ARC::R14)) { in assignCalleeSavedSpillSlots()
408 if (UseSaveRestoreFunclet && Last > ARC::R14) { in spillCalleeSavedRegisters()
425 if (UseSaveRestoreFunclet && Last > ARC::R14) { in restoreCalleeSavedRegisters()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
DMSP430RegisterInfo.td69 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td58 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
98 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
114 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/freebsd-12-stable/sys/cddl/dev/dtrace/arm/
Dregset.h46 #define REG_LINK R14
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
428 RAX, R10, R11, R13, R14, R15]>>
523 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,
599 RAX, R10, R11, R13, R14]>>
632 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,
698 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
1095 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1098 def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>;
1103 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
[all …]
DX86RegisterInfo.td186 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
392 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
437 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h76 case Lanai::R14: in getLanaiRegisterNumbering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp168 {codeview::RegisterId::R14, X86::R14}, in initLLVMToSEHAndCVRegMapping()
667 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
704 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
740 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
776 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
777 return X86::R14; in getX86SubSuperRegisterOrZero()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
395 let Defs = [R14, R15, R28] in
398 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
401 let Defs = [R14, R15, R28, P0] in
404 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
DCSKYMCTargetDesc.cpp41 unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true); in createCSKYMCAsmInfo()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
DLanaiRegisterInfo.cpp261 Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; } in getBaseRegister()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/
DCSKYRegisterInfo.td66 def R14 : CSKYReg<14, "r14", ["sp"]>, DwarfRegNum<[14]>;
152 (sequence "R%u", 29, 30), R14, R31)> {
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h184 ENTRY(R14) \
202 ENTRY(R14) \
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
Dfastmath2_ldlib_asm.S253 #define mantxl R14
/freebsd-12-stable/contrib/file/magic/Magdir/
Dcad209 # AutoCAD DWG versions R13/R14 (www.autodesk.com)
213 # AutoCAD DWG versions R12/R13/R14 (www.autodesk.com)
319 >>>>&1 search/8192 AC1014 \b, R14
/freebsd-12-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h56 #define R14 6 macro
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp88 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
DAVRDisassembler.cpp64 AVR::R12, AVR::R13, AVR::R14, AVR::R15,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.td271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
DARCDisassembler.cpp119 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,

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