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Searched refs:R12 (Results 1 – 25 of 59) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td42 def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
DARCFrameLowering.cpp158 StackSlotsUsedByFunclet = Last - ARC::R12; in emitPrologue()
270 StackSlotsUsedByFunclet = Last - ARC::R12; in emitEpilogue()
372 for (unsigned Which = Last; Which > ARC::R12; Which--) { in assignCalleeSavedSpillSlots()
385 if (I.getReg() > ARC::R12) in assignCalleeSavedSpillSlots()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
DMSP430RegisterInfo.td67 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
DMSP430ISelLowering.cpp459 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
464 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
782 unsigned R12 = MSP430::R12; in LowerReturn() local
784 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag); in LowerReturn()
786 RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout()))); in LowerReturn()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
342 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
390 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
426 // Return: could return in any GP register save RSP and R12.
518 // A SwiftError is passed in R12.
519 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
597 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
624 // A SwiftError is passed in R12.
625 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
[all …]
DX86RegisterInfo.td184 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
392 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
395 // Allocate R12 and R13 last, as these require an extra byte when
437 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td56 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
99 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
115 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/freebsd-12-stable/sys/cddl/dev/dtrace/arm/
Dregset.h47 #define REG_SP R12
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
DARMRegisterInfo.td91 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
241 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
260 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
318 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))];
355 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
371 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
522 [(add R12), (add SP)]>;
529 // Register class representing a pair of even-odd GPRs, except (R12, SP).
DARMCallingConv.td164 // The 'nest' parameter, if any, is passed in R12.
165 CCIfNest<CCAssignToReg<[R12]>>,
322 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
331 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
348 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
DARMExpandPseudoInsts.cpp1192 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1197 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1236 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1238 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1239 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1243 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1244 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1249 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1915 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
1945 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
DInstCombineAndOrXor.cpp310 Value *R11, *R12; in getMaskedTypeForICmpPair() local
312 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
315 D = R12; in getMaskedTypeForICmpPair()
316 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
317 A = R12; in getMaskedTypeForICmpPair()
326 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
330 R12 = Constant::getAllOnesValue(R1->getType()); in getMaskedTypeForICmpPair()
335 D = R12; in getMaskedTypeForICmpPair()
338 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
339 A = R12; in getMaskedTypeForICmpPair()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h72 case Lanai::R12: in getLanaiRegisterNumbering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp166 {codeview::RegisterId::R12, X86::R12}, in initLLVMToSEHAndCVRegMapping()
663 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
700 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
736 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
772 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
773 return X86::R12; in getX86SubSuperRegisterOrZero()
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
Dfastmath2_dlib_asm.S265 #define c8001 R12
272 #define mantal_ R12
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h182 ENTRY(R12) \
200 ENTRY(R12) \
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp446 Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; in findScratchRegister() local
454 *SR2 = R12; in findScratchRegister()
481 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) in findScratchRegister()
654 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue()
1574 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitEpilogue()
2435 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) in spillCalleeSavedRegisters()
2440 .addReg(PPC::R12, in spillCalleeSavedRegisters()
2499 unsigned MoveReg = PPC::R12; in restoreCRs()
/freebsd-12-stable/contrib/llvm-project/libunwind/src/
DUnwindCursor.hpp556 _msContext.R12 = r.getRegister(UNW_X86_64_R12); in UnwindCursor()
610 _msContext.R12 = r.getRegister(UNW_ARM_R12); in UnwindCursor()
676 case UNW_X86_64_R12: return _msContext.R12; in getReg()
693 case UNW_ARM_R12: return _msContext.R12; in getReg()
726 case UNW_X86_64_R12: _msContext.R12 = value; break; in setReg()
743 case UNW_ARM_R12: _msContext.R12 = value; break; in setReg()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/freebsd-12-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h54 #define R12 4 macro
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp88 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15

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