| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 156 MVT PartVT, EVT ValueVT, const Value *V,
166 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
172 PartVT, ValueVT, CC)) in getCopyFromParts()
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
185 unsigned PartBits = PartVT.getSizeInBits(); in getCopyFromParts()
200 PartVT, HalfVT, V); in getCopyFromParts()
202 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
217 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, in getCopyFromParts()
233 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1561 EVT PartVT = VT; in getVectorTypeBreakdown() local
1564 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1565 PartVT = LK.second; in getVectorTypeBreakdown()
1569 PartVT.getVectorElementCount().getKnownMinValue(); in getVectorTypeBreakdown()
1575 assert((PartVT.getVectorElementCount() * NumIntermediates) == in getVectorTypeBreakdown()
1578 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1677 MVT PartVT = in GetReturnInfo() local
1692 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.h | 481 unsigned NumParts, MVT PartVT,
487 MVT PartVT, EVT ValueVT,
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| D | RISCVISelLowering.cpp | 8005 EVT PartVT = PartValue.getValueType(); in LowerCall() local
8006 if (PartVT.isScalableVector()) in LowerCall()
8008 StoredSize += PartVT.getStoreSize(); in LowerCall()
8009 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
8980 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
8983 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
8995 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
8998 EVT PartEltVT = PartVT.getVectorElementType(); in splitValueIntoRegisterParts()
9000 unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinSize(); in splitValueIntoRegisterParts()
9011 Val = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in splitValueIntoRegisterParts()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 543 unsigned NumParts, MVT PartVT,
548 MVT PartVT, EVT ValueVT,
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| D | SystemZISelLowering.cpp | 1393 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1396 ((NumParts == 1 && PartVT == MVT::Untyped) || in splitValueIntoRegisterParts()
1397 (NumParts == 2 && PartVT == MVT::i64))) && in splitValueIntoRegisterParts()
1409 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1411 ((NumParts == 1 && PartVT == MVT::Untyped) || in joinRegisterPartsIntoValue()
1412 (NumParts == 2 && PartVT == MVT::i64))) && in joinRegisterPartsIntoValue()
1643 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1645 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 882 SDValue *Parts, unsigned NumParts, MVT PartVT,
888 MVT PartVT, EVT ValueVT,
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| D | ARMISelLowering.cpp | 4331 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4335 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4337 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4340 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4349 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4352 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4354 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 3699 unsigned NumParts, MVT PartVT, in splitValueIntoRegisterParts() argument
3708 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 502 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
504 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()
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