1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1999 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998, 1999 Eduardo E. Horvath 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 51 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 53 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 54 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from: NetBSD: psychoreg.h,v 1.14 2008/05/30 02:29:37 mrg Exp 59 * 60 * $FreeBSD: stable/12/sys/sparc64/pci/psychoreg.h 326262 2017-11-27 15:10:39Z pfg $ 61 */ 62 63 #ifndef _SPARC64_PCI_PSYCHOREG_H_ 64 #define _SPARC64_PCI_PSYCHOREG_H_ 65 66 /* 67 * Sun4u PCI definitions. Here's where we deal w/the machine 68 * dependencies of Psycho and the PCI controller on the UltraIIi. 69 * 70 * All PCI registers are bit-swapped, however they are not byte-swapped. 71 * This means that they must be accessed using little-endian access modes, 72 * either map the pages little-endian or use little-endian ASIs. 73 * 74 * PSYCHO implements two PCI buses, A and B. 75 */ 76 77 #define PSYCHO_NINTR 6 78 79 /* 80 * Psycho register offsets 81 * 82 * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000 83 * respectively. 84 */ 85 #define PSR_UPA_PORTID 0x0000 /* UPA port ID register */ 86 #define PSR_UPA_CONFIG 0x0008 /* UPA config register */ 87 #define PSR_CS 0x0010 /* PSYCHO control/status register */ 88 #define PSR_ECCC 0x0020 /* ECC control register */ 89 #define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 90 #define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 91 #define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */ 92 #define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */ 93 #define PSR_PM_CTL 0x0100 /* Performance monitor control reg */ 94 #define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */ 95 #define PSR_IOMMU 0x0200 /* IOMMU registers */ 96 #define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */ 97 #define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */ 98 #define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */ 99 #define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */ 100 #define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */ 101 #define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */ 102 #define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */ 103 #define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */ 104 #define PSR_SCSI_INT_MAP 0x1000 /* SCSI interrupt map reg */ 105 #define PSR_ETHER_INT_MAP 0x1008 /* ethernet interrupt map reg */ 106 #define PSR_BPP_INT_MAP 0x1010 /* parallel interrupt map reg */ 107 #define PSR_AUDIOR_INT_MAP 0x1018 /* audio record interrupt map reg */ 108 #define PSR_AUDIOP_INT_MAP 0x1020 /* audio playback interrupt map reg */ 109 #define PSR_POWER_INT_MAP 0x1028 /* power fail interrupt map reg */ 110 #define PSR_SKBDMS_INT_MAP 0x1030 /* serial/kbd/mouse interrupt map reg */ 111 #define PSR_FD_INT_MAP 0x1038 /* floppy interrupt map reg */ 112 #define PSR_SPARE_INT_MAP 0x1040 /* spare interrupt map reg */ 113 #define PSR_KBD_INT_MAP 0x1048 /* kbd [unused] interrupt map reg */ 114 #define PSR_MOUSE_INT_MAP 0x1050 /* mouse [unused] interrupt map reg */ 115 #define PSR_SERIAL_INT_MAP 0x1058 /* second serial interrupt map reg */ 116 #define PSR_TIMER0_INT_MAP 0x1060 /* timer 0 interrupt map reg */ 117 #define PSR_TIMER1_INT_MAP 0x1068 /* timer 1 interrupt map reg */ 118 #define PSR_UE_INT_MAP 0x1070 /* UE interrupt map reg */ 119 #define PSR_CE_INT_MAP 0x1078 /* CE interrupt map reg */ 120 #define PSR_PCIAERR_INT_MAP 0x1080 /* PCI bus a error interrupt map reg */ 121 #define PSR_PCIBERR_INT_MAP 0x1088 /* PCI bus b error interrupt map reg */ 122 #define PSR_PWRMGT_INT_MAP 0x1090 /* power mgmt wake interrupt map reg */ 123 #define PSR_FFB0_INT_MAP 0x1098 /* FFB0 graphics interrupt map reg */ 124 #define PSR_FFB1_INT_MAP 0x10a0 /* FFB1 graphics interrupt map reg */ 125 /* Note: Clear interrupt 0 registers are not really used. */ 126 #define PSR_PCIA0_INT_CLR 0x1400 /* PCI a slot 0 clear int regs 0..3 */ 127 #define PSR_PCIA1_INT_CLR 0x1420 /* PCI a slot 1 clear int regs 0..3 */ 128 #define PSR_PCIA2_INT_CLR 0x1440 /* PCI a slot 2 clear int regs 0..3 */ 129 #define PSR_PCIA3_INT_CLR 0x1460 /* PCI a slot 3 clear int regs 0..3 */ 130 #define PSR_PCIB0_INT_CLR 0x1480 /* PCI b slot 0 clear int regs 0..3 */ 131 #define PSR_PCIB1_INT_CLR 0x14a0 /* PCI b slot 1 clear int regs 0..3 */ 132 #define PSR_PCIB2_INT_CLR 0x14c0 /* PCI b slot 2 clear int regs 0..3 */ 133 #define PSR_PCIB3_INT_CLR 0x14d0 /* PCI b slot 3 clear int regs 0..3 */ 134 #define PSR_SCSI_INT_CLR 0x1800 /* SCSI clear int reg */ 135 #define PSR_ETHER_INT_CLR 0x1808 /* ethernet clear int reg */ 136 #define PSR_BPP_INT_CLR 0x1810 /* parallel clear int reg */ 137 #define PSR_AUDIOR_INT_CLR 0x1818 /* audio record clear int reg */ 138 #define PSR_AUDIOP_INT_CLR 0x1820 /* audio playback clear int reg */ 139 #define PSR_POWER_INT_CLR 0x1828 /* power fail clear int reg */ 140 #define PSR_SKBDMS_INT_CLR 0x1830 /* serial/kbd/mouse clear int reg */ 141 #define PSR_FD_INT_CLR 0x1838 /* floppy clear int reg */ 142 #define PSR_SPARE_INT_CLR 0x1840 /* spare clear int reg */ 143 #define PSR_KBD_INT_CLR 0x1848 /* kbd [unused] clear int reg */ 144 #define PSR_MOUSE_INT_CLR 0x1850 /* mouse [unused] clear int reg */ 145 #define PSR_SERIAL_INT_CLR 0x1858 /* second serial clear int reg */ 146 #define PSR_TIMER0_INT_CLR 0x1860 /* timer 0 clear int reg */ 147 #define PSR_TIMER1_INT_CLR 0x1868 /* timer 1 clear int reg */ 148 #define PSR_UE_INT_CLR 0x1870 /* UE clear int reg */ 149 #define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */ 150 #define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */ 151 #define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */ 152 #define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */ 153 #define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */ 154 #define PSR_TC0 0x1c00 /* timer/counter 0 */ 155 #define PSR_TC1 0x1c10 /* timer/counter 1 */ 156 #define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */ 157 #define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st Psycho */ 158 #define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd Psycho */ 159 #define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */ 160 #define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */ 161 #define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */ 162 #define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */ 163 #define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */ 164 #define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */ 165 #define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */ 166 #define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */ 167 #define PSR_OBIO_INT_DIAG 0xa808 /* OBIO and misc int state diag reg */ 168 #define PSR_STRBUF_DIAG 0xb000 /* Streaming buffer diag regs */ 169 170 /* 171 * Here is the rest of the map, which we're not specifying: 172 * 173 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 174 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 175 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 176 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 177 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 178 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 179 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 180 * 181 * NB: Config and I/O space can use 1-4 byte accesses, not 8 byte 182 * accesses. Memory space can use any sized accesses. 183 * 184 * Note that the SUNW,sabre/SUNW,simba combinations found on the 185 * Ultra5 and Ultra10 machines uses slightly differrent addresses 186 * than the above. This is mostly due to the fact that the APB is 187 * a multi-function PCI device with two PCI bridges, and the U2P is 188 * two separate PCI bridges. It uses the same PCI configuration 189 * space, though the configuration header for each PCI bus is 190 * located differently due to the SUNW,simba PCI busses being 191 * function 0 and function 1 of the APB, whereas the Psycho's are 192 * each their own PCI device. The I/O and memory spaces are each 193 * split into 8 equally sized areas (8x2MB blocks for I/O space, 194 * and 8x512MB blocks for memory space). These are allocated in to 195 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 196 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) 197 * registers of each Simba. We must ensure that both of the 198 * following are correct (the prom should do this for us): 199 * 200 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 201 * 202 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 203 * 204 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 205 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 206 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 207 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 208 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 209 */ 210 211 /* 212 * PSR_CS defines: 213 * 214 * 63 59 55 50 45 4 3 2 1 0 215 * +------+------+------+------+--//---+--------+-------+-----+------+ 216 * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE | 217 * +------+------+------+------+--//---+--------+-------+-----+------+ 218 * 219 */ 220 #define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf)) 221 #define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 222 #define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 223 #define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 224 #define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 225 #define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 226 #define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 227 #define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 228 229 /* Offsets into the PSR_PCICTL* register block */ 230 #define PCR_CS 0x0000 /* PCI control/status register */ 231 #define PCR_AFS 0x0010 /* PCI AFSR register */ 232 #define PCR_AFA 0x0018 /* PCI AFAR register */ 233 #define PCR_DIAG 0x0020 /* PCI diagnostic register */ 234 #define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */ 235 #define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */ 236 237 /* INO defines */ 238 #define PSYCHO_MAX_INO 0x3f 239 240 /* Device space defines */ 241 #define PSYCHO_CONF_SIZE 0x1000000 242 #define PSYCHO_CONF_BUS_SHIFT 16 243 #define PSYCHO_CONF_DEV_SHIFT 11 244 #define PSYCHO_CONF_FUNC_SHIFT 8 245 #define PSYCHO_CONF_REG_SHIFT 0 246 #define PSYCHO_IO_SIZE 0x1000000 247 #define PSYCHO_MEM_SIZE 0x100000000 248 249 #define PSYCHO_CONF_OFF(bus, slot, func, reg) \ 250 (((bus) << PSYCHO_CONF_BUS_SHIFT) | \ 251 ((slot) << PSYCHO_CONF_DEV_SHIFT) | \ 252 ((func) << PSYCHO_CONF_FUNC_SHIFT) | \ 253 ((reg) << PSYCHO_CONF_REG_SHIFT)) 254 255 /* what the bits mean! */ 256 257 /* 258 * PCI [a|b] control/status register 259 * Note that the Hummingbird/Sabre only has one set of PCI control/status 260 * registers. 261 */ 262 #define PCICTL_SBHERR 0x0000000800000000 /* strm. byte hole error; W1C */ 263 #define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 264 #define PCICTL_PCISPEED 0x0000000200000000 /* 0:half 1:full bus speed */ 265 #define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 266 #define PCICTL_SBHINTEN 0x0000000000000400 /* strm. byte hole int. en. */ 267 #define PCICTL_WAKEUPEN 0x0000000000000200 /* power mgmt. wakeup enable */ 268 #define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 269 #define PCICTL_ARB_4 0x000000000000000f /* DVMA arb. 4 PCI slots mask */ 270 #define PCICTL_ARB_6 0x000000000000003f /* DVMA arb. 6 PCI slots mask */ 271 /* The following are Hummingbird/Sabre only. */ 272 #define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */ 273 #define PCICTL_CPU_PRIO 0x0000000000100000 /* CPU extra arb. prio. en. */ 274 #define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI extra arb. prio. en. */ 275 #define PCICTL_RTRYWAIT 0x0000000000000080 /* 0:wait 1:retry DMA write */ 276 277 /* Uncorrectable error asynchronous fault status register */ 278 #define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 279 #define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */ 280 #define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */ 281 #define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */ 282 #define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */ 283 #define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */ 284 #define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */ 285 #define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */ 286 #define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */ 287 288 /* Correctable error asynchronous fault status register */ 289 #define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 290 #define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write */ 291 #define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read */ 292 #define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access */ 293 #define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write */ 294 #define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */ 295 #define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */ 296 297 /* PCI asynchronous fault status register */ 298 #define PCIAFSR_P_MA (1UL << 63) /* Pri. master abort */ 299 #define PCIAFSR_P_TA (1UL << 62) /* Pri. target abort */ 300 #define PCIAFSR_P_RTRY (1UL << 61) /* Pri. excessive retries */ 301 #define PCIAFSR_P_RERR (1UL << 60) /* Pri. parity error */ 302 #define PCIAFSR_S_MA (1UL << 59) /* Sec. master abort */ 303 #define PCIAFSR_S_TA (1UL << 58) /* Sec. target abort */ 304 #define PCIAFSR_S_RTRY (1UL << 57) /* Sec. excessive retries */ 305 #define PCIAFSR_S_RERR (1UL << 56) /* Sec. parity error */ 306 #define PCIAFSR_BMASK (0xffffUL << 32)/* Bytemask of failed pri. transfer */ 307 #define PCIAFSR_BLK (1UL << 31) /* failed pri. transfer was block r/w */ 308 #define PCIAFSR_MID (0x3eUL << 25) /* UPA MID causing error transaction */ 309 310 /* PCI diagnostic register */ 311 #define DIAG_RTRY_DIS 0x0000000000000040 /* dis. retry limit */ 312 #define DIAG_ISYNC_DIS 0x0000000000000020 /* dis. DMA write / int sync */ 313 #define DIAG_DWSYNC_DIS 0x0000000000000010 /* dis. DMA write / PIO sync */ 314 315 /* Definitions for the target address space register */ 316 #define PCITAS_ADDR_SHIFT 29 317 318 /* Definitions for the Psycho configuration space */ 319 #define PCS_DEVICE 0 /* Device number of Psycho CS entry */ 320 #define PCS_FUNC 0 /* Function number of Psycho CS entry */ 321 322 /* Non-Standard registers in the configration space */ 323 #define PCSR_SECBUS 0x40 /* Secondary bus number register */ 324 #define PCSR_SUBBUS 0x41 /* Subordinate bus number register */ 325 326 /* Width of the physical addresses the IOMMU translates to */ 327 #define PSYCHO_IOMMU_BITS 41 328 #define SABRE_IOMMU_BITS 34 329 330 #endif /* !_SPARC64_PCI_PSYCHOREG_H_ */ 331