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Searched refs:PLL (Results 1 – 25 of 42) sorted by relevance

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/freebsd-12-stable/sys/arm/nvidia/tegra124/
Dtegra124_clk_pll.c119 #define PLL(_id, cname, pname) \ macro
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
[all …]
/freebsd-12-stable/sys/arm64/rockchip/clk/
Drk3399_cru.c695 #define PLL(_id, _name, _base) \ macro
798 PLL(PLL_APLLL, "lpll", 0x00),
799 PLL(PLL_APLLB, "bpll", 0x20),
800 PLL(PLL_DPLL, "dpll", 0x40),
801 PLL(PLL_CPLL, "cpll", 0x60),
802 PLL(PLL_GPLL, "gpll", 0x80),
803 PLL(PLL_NPLL, "npll", 0xA0),
804 PLL(PLL_VPLL, "vpll", 0xC0),
/freebsd-12-stable/sys/gnu/dts/arm/
Dvexpress-v2p-ca15-tc1.dts146 /* CPU PLL reference clock */
164 /* HDLCD PLL reference clock */
182 /* SYS PLL reference clock */
191 /* DDR2 PLL reference clock */
Dvexpress-v2p-ca15_a7.dts257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
302 /* HDLCD PLL reference clock */
320 /* SYS PLL reference clock */
329 /* DDR2 PLL reference clock */
Ddra62x-clocks.dtsi18 /* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
Dam3874-iceboard.dts354 /* The PLL doesn't react well to the SPI controller reset, so
369 DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
370 DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
Dbcm-cygnus-clock.dtsi44 /* Cygnus ARM PLL */
Dstih416-clock.dtsi498 * A9 PLL
726 * DDR PLL
742 * GPU PLL
Darmada-370-xp.dtsi308 /* 2 GHz fixed main PLL */
Dstih410-clock.dtsi31 * A9 PLL.
Dstih407-clock.dtsi28 * A9 PLL.
Dstih418-clock.dtsi31 * A9 PLL.
Darm-realview-eb.dtsi110 /* FIXME: this actually hangs off the PLL clocks */
Darmada-39x.dtsi544 /* 1 GHz fixed main PLL */
Darm-realview-pbx.dtsi125 /* FIXME: this actually hangs off the PLL clocks */
/freebsd-12-stable/sys/mips/ingenic/
Djz4780_clock.c82 #define PLL(_id, cname, pname, reg) { \ macro
140 PLL(JZ4780_CLK_APLL, "apll", "ext", JZ_CPAPCR),
141 PLL(JZ4780_CLK_MPLL, "mpll", "ext", JZ_CPMPCR),
142 PLL(JZ4780_CLK_EPLL, "epll", "ext", JZ_CPEPCR),
143 PLL(JZ4780_CLK_VPLL, "vpll", "ext", JZ_CPVPCR),
/freebsd-12-stable/contrib/ntp/html/hints/
Dlinux1 The kernel PLL interface is broken, I know.
Dsolaris.xtra.40958495 Synopsis: time_constant value >6 with PLL in use leads to integer divide
30 is done without the PLL algorithm in the kernel.
/freebsd-12-stable/sys/dev/bhnd/cores/pmu/
Dbhnd_pmu_if.m203 * Return the current value of a PMU PLL control register.
219 * Write @p value with @p mask to a PMU PLL control register.
/freebsd-12-stable/sys/dev/bktr/
DCHANGELOG.TXT218 with single crystal PLL configuration
246 PAL/SECAM boards will use PLL mode.
407 Tidy up a few tables with tabs and PLL selection code.
408 Restore Video Highway Xtreme PLL code.
420 Make PLL mode the default for Bt878 chips. This means PAL
/freebsd-12-stable/sys/mips/conf/
DTL-WR1043NDv2.hints103 # if_arge thus wont change the PLL configuration
DAP135.hints88 # if_arge thus wont change the PLL configuration
DDIR-655A1.hints113 # if_arge thus wont change the PLL configuration
DTL-ARCHERC7V2.hints105 # if_arge thus wont change the PLL configuration
/freebsd-12-stable/sys/gnu/dts/arm64/freescale/
Dimx8mq-evk.dts123 * On imx8mq B0 PLL can't be bypassed so low bus is 166M

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