| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86ShuffleDecode.cpp | 149 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
150 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
151 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
220 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKHMask() local
221 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
222 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
236 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKLMask() local
237 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
238 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
266 unsigned NumLanes = NumElts / NumElementsInLane; in decodeVSHUF64x2FamilyMask() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 303 unsigned NumLanes = Size / 4; in allocateSGPRSpillToVGPR() local
305 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPR()
313 for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) { in allocateSGPRSpillToVGPR()
400 unsigned NumLanes = Size / 4; in allocateVGPRSpillToAGPR() local
401 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
429 for (unsigned I = 0; I < NumLanes; ++I) { in allocateVGPRSpillToAGPR()
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| D | AMDGPURegisterBankInfo.cpp | 1991 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect() local
1992 if (!NumLanes) in foldExtractEltToCmpSelect()
1993 NumLanes = 1; in foldExtractEltToCmpSelect()
1998 SmallVector<Register, 2> Res(NumLanes); in foldExtractEltToCmpSelect()
1999 for (unsigned L = 0; L < NumLanes; ++L) in foldExtractEltToCmpSelect()
2008 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
2010 UnmergeToEltTy.getReg(I * NumLanes + L), Res[L]); in foldExtractEltToCmpSelect()
2019 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
2020 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; in foldExtractEltToCmpSelect()
2092 unsigned NumLanes = InsRegs.size(); in foldInsertEltToCmpSelect() local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 2225 int NumLanes = 1; in addConstantComments() local
2228 case X86::VBROADCASTF128: NumLanes = 2; break; in addConstantComments()
2229 case X86::VBROADCASTI128: NumLanes = 2; break; in addConstantComments()
2230 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; in addConstantComments()
2231 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; in addConstantComments()
2232 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; in addConstantComments()
2233 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; in addConstantComments()
2234 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; in addConstantComments()
2235 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; in addConstantComments()
2236 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break; in addConstantComments()
[all …]
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| D | X86InstCombineIntrinsic.cpp | 449 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
454 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
492 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
1953 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in simplifyDemandedVectorEltsIntrinsic() local
1954 unsigned VWidthPerLane = VWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1955 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1963 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
1978 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
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| D | X86InterleavedAccess.cpp | 481 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
482 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
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| D | X86ISelLowering.cpp | 6897 unsigned NumLanes = VT.getSizeInBits() / 128; in createPackShuffleMask() local
6904 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask()
6917 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
6920 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
6921 int NumInnerEltsPerLane = NumInnerElts / NumLanes; in getPackDemandedElts()
6927 for (int Lane = 0; Lane != NumLanes; ++Lane) { in getPackDemandedElts()
6942 int NumLanes = VT.getSizeInBits() / 128; in getHorizDemandedElts() local
6944 int NumEltsPerLane = NumElts / NumLanes; in getHorizDemandedElts()
10937 int NumLanes = NumElts / NumEltsPerLane; in isMultiLaneShuffleMask() local
10938 if (NumLanes > 1) { in isMultiLaneShuffleMask()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.h | 158 template <unsigned NumLanes, char LaneKind>
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| D | AArch64InstPrinter.cpp | 1434 template <unsigned NumLanes, char LaneKind>
1439 if (NumLanes) in printTypedVectorList()
1440 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 942 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in clearUsed() local
1267 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in getBestLaneToStartReordering() local
1305 unsigned NumLanes = VL.size(); in appendOperandsOfVL() local
1307 OpsVec[OpIdx].resize(NumLanes); in appendOperandsOfVL()
1308 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in appendOperandsOfVL()
1396 unsigned NumLanes = getNumLanes(); in reorder() local
1455 for (unsigned Distance = 1; Distance != NumLanes; ++Distance) { in reorder()
1459 if (Lane < 0 || Lane >= (int)NumLanes) in reorder()
1462 assert(LastLane >= 0 && LastLane < (int)NumLanes && in reorder()
1691 unsigned NumLanes = Scalars.size(); in setOperandsInOrder() local
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| /freebsd-12-stable/contrib/llvm-project/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 767 unsigned NumLanes; in fromTypedefName() local
768 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
770 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| D | AutoUpgrade.cpp | 2474 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in UpgradeIntrinsicCall() local
2476 unsigned ControlBitsMask = NumLanes - 1; in UpgradeIntrinsicCall()
2477 unsigned NumControlBits = NumLanes / 2; in UpgradeIntrinsicCall()
2480 for (unsigned l = 0; l != NumLanes; ++l) { in UpgradeIntrinsicCall()
2483 if (l >= NumLanes / 2) in UpgradeIntrinsicCall()
2484 LaneMask += NumLanes; in UpgradeIntrinsicCall()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 2085 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements(); in unrollVectorShift() local
2093 for (size_t i = 0; i < NumLanes; ++i) { in unrollVectorShift()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 12850 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local
12851 switch (NumLanes) { in performFpToIntCombine()
12923 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
12924 switch (NumLanes) { in performFDivCombine()
16843 uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue(); in PerformDAGCombine() local
16844 SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL); in PerformDAGCombine()
16860 uint64_t NumLanes = in PerformDAGCombine() local
16863 if ((TupleLanes % NumLanes) != 0) in PerformDAGCombine()
16866 uint64_t NumVecs = TupleLanes / NumLanes; in PerformDAGCombine()
16873 SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL); in PerformDAGCombine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 722 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
723 let Name = "MVEVectorIndex"#NumLanes;
725 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
728 class MVEVectorIndex<int NumLanes> : Operand<i32> {
730 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
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| D | ARMISelLowering.cpp | 15880 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
15881 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVCVTCombine()
15900 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
15938 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
15939 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVDIVCombine()
15958 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 13363 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13364 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13389 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13390 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13496 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
13497 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13501 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
13502 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2215 template <unsigned NumLanes>
2218 return VectorIndex.Val < NumLanes; in isVectorIndexInRange()
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