| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction()
87 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction()
91 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegister.h | 42 static constexpr unsigned NoRegister = 0u; variable
67 assert(Val == NoRegister || isPhysicalRegister(Val)); in from()
75 bool isValid() const { return Reg != NoRegister; } in isValid()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| D | AVRAsmParser.cpp | 344 if (RegNum == AVR::NoRegister) { in parseRegisterName()
347 if (RegNum == AVR::NoRegister) { in parseRegisterName()
357 if (RegNum == AVR::NoRegister) in parseRegisterName()
364 int RegNum = AVR::NoRegister; in parseRegister()
378 if (RegNum == AVR::NoRegister && RestoreOnFailure) { in parseRegister()
392 if (RegNo == AVR::NoRegister) in tryParseRegisterOperand()
567 if (RegNo == AVR::NoRegister) in parseMemriOperand()
593 return (RegNo == AVR::NoRegister); in ParseRegister()
603 if (RegNo == AVR::NoRegister) in tryParseRegister()
726 if (RegNum != AVR::NoRegister) { in validateTargetOperandClass()
[all …]
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUResourceUsageAnalysis.cpp | 170 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
179 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
186 Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
191 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
201 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
204 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
247 case AMDGPU::NoRegister: in analyzeResourceUsage()
|
| D | R600RegisterInfo.cpp | 68 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
76 return R600::NoRegister; in getFrameRegister()
|
| D | SIRegisterInfo.cpp | 88 Register TmpVGPR = AMDGPU::NoRegister;
94 Register SavedExecReg = AMDGPU::NoRegister;
357 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
542 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
946 if (Reg == AMDGPU::NoRegister) in spillVGPRtoAGPR()
1131 if (ScratchOffsetReg == AMDGPU::NoRegister) { in buildSpillLoadStore()
1142 if (IsFlat && SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1254 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1270 if (!IsStore && TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore()
1895 if (FrameReg != AMDGPU::NoRegister) in eliminateFrameIndex()
[all …]
|
| D | SIOptimizeExecMasking.cpp | 69 return AMDGPU::NoRegister; in isCopyFromExec()
131 return AMDGPU::NoRegister; in isLogicalOpOnExec()
|
| D | SIMachineFunctionInfo.cpp | 328 if (LaneVGPR == AMDGPU::NoRegister) { in allocateSGPRSpillToVGPR()
401 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
647 this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister; in removeVGPRForSGPRSpill()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | MVETailPredUtils.h | 113 MIB.addReg(ARM::NoRegister);
121 MIB.addReg(ARM::NoRegister);
178 MIB.addReg(ARM::NoRegister);
|
| D | Thumb1FrameLowering.cpp | 79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
184 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
197 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
378 unsigned ScratchRegister = ARM::NoRegister; in emitPrologue()
493 NumBytes - ArgRegsSaveSize, ARM::NoRegister, in emitEpilogue()
532 unsigned ScratchRegister = ARM::NoRegister; in emitEpilogue()
737 ArgRegsSaveSize + 4, ARM::NoRegister, in emitPopSpecialFixUp()
780 ARM::NoRegister, MachineInstr::NoFlags); in emitPopSpecialFixUp()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| D | VEDisassembler.cpp | 118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
170 unsigned Reg = VE::NoRegister; in DecodeV64RegisterClass()
207 if (Reg == VE::NoRegister) in DecodeMISCRegisterClass()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| D | VEAsmParser.cpp | 132 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
133 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
135 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
683 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister) in MorphToMISCReg()
812 if (RegNum == VE::NoRegister) { in parseRegisterName()
838 if (RegNo == VE::NoRegister) in tryParseRegister()
841 if (RegNo != VE::NoRegister) { in tryParseRegister()
1280 unsigned BaseReg = VE::NoRegister; in parseMEMAsOperand()
1318 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1324 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
[all …]
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | Register.h | 121 assert(Reg == MCRegister::NoRegister || in asMCReg()
126 bool isValid() const { return Reg != MCRegister::NoRegister; } in isValid()
|
| D | LiveRegMatrix.h | 140 MCRegister PhysReg = MCRegister::NoRegister);
|
| D | RegisterClassInfo.h | 119 return MCRegister::NoRegister; in getLastCalleeSavedAlias()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | LVLGen.cpp | 57 return VE::NoRegister; in getVL()
78 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 496 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
511 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
674 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegsRegisterClass()
675 if (CtrlRegDecoderTable[RegNo] == NoRegister) in DecodeCtrRegsRegisterClass()
702 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegs64RegisterClass()
703 if (CtrlReg64DecoderTable[RegNo] == NoRegister) in DecodeCtrRegs64RegisterClass()
781 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) in DecodeGuestRegsRegisterClass()
807 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) in DecodeGuestRegs64RegisterClass()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86AvoidStoreForwardingBlocks.cpp | 320 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) in isRelevantAddressingMode()
326 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
328 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
403 .addReg(X86::NoRegister) in buildCopy()
405 .addReg(X86::NoRegister) in buildCopy()
422 .addReg(X86::NoRegister) in buildCopy()
424 .addReg(X86::NoRegister) in buildCopy()
|
| D | X86LoadValueInjectionRetHardening.cpp | 83 if (ClobberReg != X86::NoRegister) { in runOnMachineFunction()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 35 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
91 unsigned PredReg = Hexagon::NoRegister; in init()
132 unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister; in init()
445 if (std::get<2>(Producer).Register != Hexagon::NoRegister && in checkNewValues()
547 (ProducerPredicate.Register == Hexagon::NoRegister || in registerProducer()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 83 Register InReg = PPC::NoRegister; in processBlock()
161 assert(InReg != PPC::NoRegister && "Operand must be a register"); in processBlock()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInsertVSETVLI.cpp | 193 if (InstrInfo.hasAVLReg() && InstrInfo.AVLReg == RISCV::NoRegister) { in isCompatible()
400 InstrInfo.setAVLReg(RISCV::NoRegister); in computeInfoForInstr()
433 if (AVLReg == RISCV::NoRegister) { in insertVSETVLI()
658 VLOp.setReg(RISCV::NoRegister); in emitVSETVLIs()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
614 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
638 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
675 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
711 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
786 assert(Res != X86::NoRegister && "Unexpected register or VT"); in getX86SubSuperRegister()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2123 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), in processInstruction()
2388 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, in tryExpandInstruction()
2725 if (SrcReg != Mips::NoRegister) in loadImmediate()
2832 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, in loadImmediate()
2869 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2913 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && in loadAndAddSymbolAddress()
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3397 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, in expandLoadSingleImmToFPR()
3443 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
[all …]
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2281 .Default(AMDGPU::NoRegister); in getSpecialRegForName()
2427 return getSpecialRegForName(Str) != AMDGPU::NoRegister; in isRegister()
2453 return AMDGPU::NoRegister; in getRegularReg()
2460 return AMDGPU::NoRegister; in getRegularReg()
2467 return AMDGPU::NoRegister; in getRegularReg()
2541 return AMDGPU::NoRegister; in ParseRegularReg()
2553 return AMDGPU::NoRegister; in ParseRegularReg()
2559 return AMDGPU::NoRegister; in ParseRegularReg()
2568 unsigned Reg = AMDGPU::NoRegister; in ParseRegList()
2573 return AMDGPU::NoRegister; in ParseRegList()
[all …]
|