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Searched refs:NewRC (Results 1 – 25 of 32) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp74 const TargetRegisterClass *NewRC = in constrainRegClass() local
76 if (!NewRC || NewRC == OldRC) in constrainRegClass()
77 return NewRC; in constrainRegClass()
78 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
81 return NewRC; in constrainRegClass()
125 const TargetRegisterClass *NewRC = in recomputeRegClass() local
129 if (NewRC == OldRC) in recomputeRegClass()
137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
139 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
DCriticalAntiDepBreaker.cpp187 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
190 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
194 if (!Classes[Reg] && NewRC) in PrescanInstruction()
195 Classes[Reg] = NewRC; in PrescanInstruction()
196 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
315 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
317 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
321 if (!Classes[Reg] && NewRC) in ScanInstruction()
322 Classes[Reg] = NewRC; in ScanInstruction()
323 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
DRegisterCoalescer.h57 const TargetRegisterClass *NewRC = nullptr; variable
81 bool isPhys() const { return !NewRC; } in isPhys()
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
DRegisterCoalescer.cpp460 NewRC = nullptr; in setRegisters()
506 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
508 if (!NewRC) in setRegisters()
513 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
517 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
520 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
524 if (!NewRC) in setRegisters()
535 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1375 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1385 NewRC = CommonRC; in reMaterializeTrivialDef()
[all …]
DTailDuplicator.cpp447 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
448 if (NewRC == nullptr) in duplicateInstruction()
449 NewRC = OrigRC; in duplicateInstruction()
450 Register NewReg = MRI->createVirtualRegister(NewRC); in duplicateInstruction()
DPeepholeOptimizer.cpp781 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
785 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/
DLazyCallGraph.cpp1651 RefSCC *NewRC = OriginalRC; in addSplitFunction() local
1652 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1661 int InsertIndex = EK == Edge::Kind::Call ? NewRC->SCCIndices[OriginalC] in addSplitFunction()
1662 : NewRC->SCCIndices.size(); in addSplitFunction()
1663 NewRC->SCCs.insert(NewRC->SCCs.begin() + InsertIndex, NewC); in addSplitFunction()
1664 for (int I = InsertIndex, Size = NewRC->SCCs.size(); I < Size; ++I) in addSplitFunction()
1665 NewRC->SCCIndices[NewRC->SCCs[I]] = I; in addSplitFunction()
1676 RefSCC *NewRC = createRefSCC(*this); in addSplitFunction() local
1677 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1678 NewRC->SCCIndices[NewC] = 0; in addSplitFunction()
[all …]
DCGSCCPassManager.cpp1072 for (RefSCC *NewRC : llvm::reverse(llvm::drop_begin(NewRefSCCs))) { in updateCGAndAnalysisManagerForPass()
1073 assert(NewRC != RC && "Should not encounter the current RefSCC further " in updateCGAndAnalysisManagerForPass()
1075 UR.RCWorklist.insert(NewRC); in updateCGAndAnalysisManagerForPass()
1077 << *NewRC << "\n"); in updateCGAndAnalysisManagerForPass()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp284 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
286 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
DAVRRegisterInfo.h59 const TargetRegisterClass *NewRC,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp381 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
386 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
432 if (NewRC->contains(*SI)) { in shouldCoalesce()
441 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
DSystemZRegisterInfo.h162 const TargetRegisterClass *NewRC,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.h61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
DHexagonVLIWPacketizer.h143 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
DHexagonRegisterInfo.cpp350 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
357 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
DHexagonFrameLowering.cpp2244 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots() argument
2245 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots()
2246 return NewRC; in optimizeSpillSlots()
2248 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2250 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
2251 return NewRC; in optimizeSpillSlots()
DHexagonBitSimplify.cpp2628 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2630 NewRC[I] = BitTracker::BitValue(C & 1); in simplifyRCmp0()
2633 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2696 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2697 NewRC[0] = BitTracker::BitValue::self(); in simplifyRCmp0()
2698 NewRC.fill(1, W, BitTracker::BitValue::Zero); in simplifyRCmp0()
2699 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
DHexagonVLIWPacketizer.cpp362 const TargetRegisterClass *NewRC) { in isNewifiable() argument
365 if (NewRC == &Hexagon::PredRegsRegClass) { in isNewifiable()
DHexagonConstPropagation.cpp2904 const TargetRegisterClass *NewRC; in rewriteHexConstDefs() local
2911 NewRC = &Hexagon::IntRegsRegClass; in rewriteHexConstDefs()
2913 NewRC = &Hexagon::DoubleRegsRegClass; in rewriteHexConstDefs()
2914 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.h135 unsigned DstSubReg, const TargetRegisterClass *NewRC,
DAArch64RegisterInfo.cpp787 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h210 const TargetRegisterClass *NewRC,
DARMBaseRegisterInfo.cpp865 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
875 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
880 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h249 const TargetRegisterClass *NewRC,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h1032 const TargetRegisterClass *NewRC, in shouldCoalesce() argument

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