Searched refs:NewBaseReg (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 255 unsigned NewBaseReg = Add.getOperand(0).getReg(); in tryToCombine() local
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2728 static void AdjustBaseAndOffset(MachineInstr *MI, Register NewBaseReg, in AdjustBaseAndOffset() argument
2733 MI->getOperand(BaseOp).setReg(NewBaseReg); in AdjustBaseAndOffset()
2739 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
2888 Register NewBaseReg; in DistributeIncrements() local
2931 NewBaseReg = PrePostInc->getOperand(0).getReg(); in DistributeIncrements()
2972 NewBaseReg = Increment->getOperand(0).getReg(); in DistributeIncrements()
2974 createPostIncLoadStore(BaseAccess, IncrementOffset, NewBaseReg, TII, TRI); in DistributeIncrements()
2983 AdjustBaseAndOffset(Use, NewBaseReg, IncrementOffset, TII, TRI); in DistributeIncrements()
2989 for (MachineOperand &Op : MRI->use_nodbg_operands(NewBaseReg)) in DistributeIncrements()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 2839 unsigned NewBaseReg = 0; in fixupRegisterOverlaps() local
2856 NewMI->getOperand(BasePos).setReg(NewBaseReg); in fixupRegisterOverlaps()
2866 NewBaseReg = 0; in fixupRegisterOverlaps()
2876 NewBaseReg = MI->getOperand(i).getReg(); in fixupRegisterOverlaps()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 4101 const SCEV *NewBaseReg = SE.getAnyExtendExpr(BaseReg, SrcTy); in GenerateTruncates() local
4102 if (NewBaseReg->isZero()) { in GenerateTruncates()
4106 BaseReg = NewBaseReg; in GenerateTruncates()
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