| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 34 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
66 def : PatGprGpr<mulhu, MULHU>;
102 // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
107 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
114 (ADDIW (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32)), 0)>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 211 case ISD::MULHU: { in trySelect()
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
|
| D | MipsSEISelLowering.cpp | 186 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
197 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
234 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
281 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 614 MULHU, enumerator
|
| D | TargetLowering.h | 2445 case ISD::MULHU: in isCommutativeBinOp()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 435 setOperationAction(ISD::MULHU, MVT::i16, Expand); in AMDGPUTargetLowering()
439 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
467 setOperationAction(ISD::MULHU, VT, Expand); in AMDGPUTargetLowering()
601 setTargetDAGCombine(ISD::MULHU); in AMDGPUTargetLowering()
1895 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
1910 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
1924 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2066 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2069 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
4100 case ISD::MULHU: in PerformDAGCombine()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 387 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
838 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1058 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 117 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
179 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
2076 case ISD::MULHU: in LowerHvxOperation()
2116 case ISD::MULHU: return LowerHvxMulh(Op, DAG); in LowerHvxOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 123 setOperationAction(ISD::MULHU, MVT::i8, Promote); in MSP430TargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 111 setOperationAction(ISD::MULHU, MVT::i32, Legal); in ARCTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 232 case ISD::MULHU: return "mulhu"; in getOperationName()
|
| D | LegalizeDAG.cpp | 3257 case ISD::MULHU: in ExpandNode()
3260 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3275 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3313 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); in ExpandNode()
|
| D | LegalizeVectorOps.cpp | 367 case ISD::MULHU: in LegalizeOp()
|
| D | TargetLowering.cpp | 5386 if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization)) in BuildUDIV()
5387 return DAG.getNode(ISD::MULHU, dl, VT, X, Y); in BuildUDIV()
6294 isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL_LOHI()
6320 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); in expandMUL_LOHI()
8185 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; in expandFixedPointMul()
8456 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in expandMULO()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 107 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 114 setOperationAction(ISD::MULHU, MVT::i32, Expand); in LanaiTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1660 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1683 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 1339 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) { in getArithmeticInstrCost()
|
| D | AArch64ISelLowering.cpp | 526 setOperationAction(ISD::MULHU, MVT::i32, Expand); in AArch64TargetLowering()
1095 setOperationAction(ISD::MULHU, VT, Legal); in AArch64TargetLowering()
1098 setOperationAction(ISD::MULHU, VT, Expand); in AArch64TargetLowering()
1167 setOperationAction(ISD::MULHU, VT, Custom); in AArch64TargetLowering()
1340 setOperationAction(ISD::MULHU, MVT::v1i64, Custom); in AArch64TargetLowering()
1341 setOperationAction(ISD::MULHU, MVT::v2i64, Custom); in AArch64TargetLowering()
1559 setOperationAction(ISD::MULHU, VT, Custom); in addTypeForFixedLengthSVE()
3063 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
4892 case ISD::MULHU: in LowerOperation()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 179 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 100 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 139 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 173 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/ |
| D | M68kISelLowering.cpp | 86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 371 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
|