Searched refs:MTC1 (Results 1 – 9 of 9) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 122 Opc = Mips::MTC1; in copyPhysReg()
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
829 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsInstructionSelector.cpp | 603 MachineInstrBuilder MTC1 = in select() local
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
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| D | MipsAsmPrinter.cpp | 883 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 564 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
937 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
938 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
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| D | MipsScheduleP5600.td | 564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| D | MipsFastISel.cpp | 396 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
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| D | MipsScheduleGeneric.td | 872 MFHC1_D64, MTC1, MTC1_D64,
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| D | MipsSEISelLowering.cpp | 3776 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3530 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3534 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
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