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Searched refs:MRMSrcReg (Results 1 – 21 of 21) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrExtension.td39 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
47 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
55 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
65 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
73 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
81 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
94 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
97 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
114 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
124 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
[all …]
DX86InstrMMX.td37 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
76 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
110 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
126 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
137 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
161 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
184 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
201 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
[all …]
DX86InstrKL.td21 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
28 def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
34 def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
72 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
95 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
340 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
778 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
785 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
794 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
801 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrMPX.td37 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
40 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
48 def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
DX86InstrXOP.td14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
56 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
67 def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
118 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
142 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
171 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
248 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
284 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
[all …]
DX86InstrSystem.td34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
133 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
136 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
152 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
155 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
198 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
200 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
202 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
[all …]
DX86InstrFMA.td39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
272 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst),
422 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst),
457 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst),
526 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrVMX.td67 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
70 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrAVX512.td528 defm rr : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
797 def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
1174 def rr : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst), (ins SrcInfo.RC:$src),
1182 def rrkz : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1195 def rrk : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1315 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
1327 defm rr : AVX512_maskable_custom<opc, MRMSrcReg,
1675 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1703 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1825 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
[all …]
DX86Instr3DNow.td32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
DX86InstrArithmetic.td154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
164 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
201 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
207 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
213 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
219 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
225 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
231 def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
676 : ITy<opcode, MRMSrcReg, typeinfo,
[all …]
DX86InstrInfo.td1488 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1496 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1504 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1513 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1521 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1529 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1779 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1782 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1785 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1788 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
[all …]
DX86InstrFormats.td45 def MRMSrcReg : Format<41>;
DX86MCInstLower.cpp965 (TSFlags & X86II::FormMask) == X86II::MRMSrcReg && in Lower()
DX86InstrShiftRotate.td875 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h118 MRMSrcReg = 41, enumerator
DX86RecognizableInstr.cpp104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); in RecognizableInstr()
546 case X86Local::MRMSrcReg: in emitInstructionSpecifier()
774 case X86Local::MRMSrcReg: in emitDecodePath()
DX86FoldTablesEmitter.cpp442 RegFormNum == X86Local::MRMSrcReg) || in areOppositeForms()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h690 MRMSrcReg = 41, enumerator
1123 case X86II::MRMSrcReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1018 case X86II::MRMSrcReg: { in emitVEXOpcodePrefix()
1252 case X86II::MRMSrcReg: in emitREXPrefix()
1535 case X86II::MRMSrcReg: { in encodeInstruction()