Searched refs:MOVN (Results 1 – 7 of 7) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
322 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOpSubword()
334 MOVN = Mips::MOVN_I_I; in expandAtomicBinOpSubword()
460 unsigned MOVIncr = IsMax ? MOVN : MOVZ; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
596 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOp()
611 MOVN = Mips::MOVN_I_I; in expandAtomicBinOp()
626 MOVN = Mips::MOVN_I64_I64; in expandAtomicBinOp()
746 unsigned MOVIncr = IsMax ? MOVN : MOVZ; in expandAtomicBinOp()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 20 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedA55.td | 63 def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 132 // MOVN,MOVZ,MOVK
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| D | AArch64SchedFalkorDetails.td | 1234 def : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^MOVN(W|X)i$")>; // imm fwd
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| D | AArch64InstrInfo.td | 1341 defm MOVN : MoveImmediate<0b00, "movn">;
1405 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
1406 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
1408 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
1409 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
1410 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
1411 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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| /freebsd-12-stable/contrib/gcc/config/mips/ |
| D | mips-ps-3d.md | 57 /* We can only support MOVN.PS and MOVZ.PS.
58 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
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