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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 39) sorted by relevance

12

/freebsd-12-stable/sys/dev/mlx5/mlx5_core/
Dmlx5_transobj.c35 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; in mlx5_alloc_transport_domain()
36 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; in mlx5_alloc_transport_domain()
52 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0}; in mlx5_dealloc_transport_domain()
53 u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0}; in mlx5_dealloc_transport_domain()
64 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; in mlx5_core_create_rq()
78 u32 out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; in mlx5_core_modify_rq()
87 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0}; in mlx5_core_destroy_rq()
88 u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0}; in mlx5_core_destroy_rq()
98 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; in mlx5_core_query_rq()
109 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; in mlx5_core_create_sq()
[all …]
Dmlx5_port.c72 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
85 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {}; in mlx5_query_pcam_reg()
97 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {}; in mlx5_query_mcam_reg()
148 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_ptys()
165 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_cap()
184 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_autoneg()
201 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_set_port_autoneg()
202 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_set_port_autoneg()
229 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_admin()
248 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_eth_proto_oper()
[all …]
Dmlx5_fw.c35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)]; in mlx5_cmd_query_adapter()
94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]; in mlx5_core_query_special_contexts()
95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)]; in mlx5_core_query_special_contexts()
239 u32 in[MLX5_ST_SZ_DW(init_hca_in)]; in mlx5_cmd_init_hca()
240 u32 out[MLX5_ST_SZ_DW(init_hca_out)]; in mlx5_cmd_init_hca()
252 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_teardown_hca()
253 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_teardown_hca()
261 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_force_teardown_hca()
262 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_force_teardown_hca()
291 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; in mlx5_cmd_fast_teardown_hca()
[all …]
Dmlx5_fs_cmd.c41 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {0}; in mlx5_cmd_update_root_ft()
42 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {0}; in mlx5_cmd_update_root_ft()
60 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5_cmd_fs_create_ft()
61 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5_cmd_fs_create_ft()
90 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5_cmd_fs_destroy_ft()
91 u32 out[MLX5_ST_SZ_DW(destroy_flow_table_out)] = {0}; in mlx5_cmd_fs_destroy_ft()
114 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in mlx5_cmd_fs_create_fg()
141 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {0}; in mlx5_cmd_fs_destroy_fg()
142 u32 out[MLX5_ST_SZ_DW(destroy_flow_group_out)] = {0}; in mlx5_cmd_fs_destroy_fg()
170 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0}; in mlx5_cmd_fs_set_fte()
[all …]
Dmlx5_qp.c125 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; in mlx5_core_create_qp()
126 u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)] = {0}; in mlx5_core_create_qp()
127 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {0}; in mlx5_core_create_qp()
158 u32 out[MLX5_ST_SZ_DW(destroy_qp_out)] = {0}; in mlx5_core_destroy_qp()
159 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {0}; in mlx5_core_destroy_qp()
316 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {0}; in mlx5_core_qp_query()
327 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {0}; in mlx5_core_xrcd_alloc()
328 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {0}; in mlx5_core_xrcd_alloc()
341 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {0}; in mlx5_core_xrcd_dealloc()
342 u32 out[MLX5_ST_SZ_DW(dealloc_xrcd_out)] = {0}; in mlx5_core_xrcd_dealloc()
[all …]
Dmlx5_mr.c59 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; in mlx5_core_create_mkey_cb()
125 u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0}; in mlx5_core_destroy_mkey()
126 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0}; in mlx5_core_destroy_mkey()
148 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0}; in mlx5_core_query_mkey()
161 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0}; in mlx5_core_dump_fill_mkey()
162 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0}; in mlx5_core_dump_fill_mkey()
188 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0}; in mlx5_core_create_psv()
189 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0}; in mlx5_core_create_psv()
213 u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0}; in mlx5_core_destroy_psv()
214 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {0}; in mlx5_core_destroy_psv()
Dmlx5_pd.c35 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; in mlx5_core_alloc_pd()
36 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; in mlx5_core_alloc_pd()
52 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0}; in mlx5_core_dealloc_pd()
53 u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0}; in mlx5_core_dealloc_pd()
Dmlx5_mcg.c36 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0}; in mlx5_core_attach_mcg()
37 u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0}; in mlx5_core_attach_mcg()
50 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0}; in mlx5_core_detach_mcg()
51 u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0}; in mlx5_core_detach_mcg()
Dmlx5_cq.c129 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_create_cq()
130 u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_create_cq()
167 u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_destroy_cq()
168 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_destroy_cq()
194 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; in mlx5_core_query_cq()
207 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0}; in mlx5_core_modify_cq()
219 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; in mlx5_core_modify_cq_moderation()
239 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; in mlx5_core_modify_cq_moderation_mode()
Dmlx5_mpfs.c47 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {}; in mlx5_mpfs_add_mac()
48 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {}; in mlx5_mpfs_add_mac()
89 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {}; in mlx5_mpfs_del_mac()
90 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {}; in mlx5_mpfs_del_mac()
Dmlx5_vport.c40 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {0}; in _mlx5_query_vport_state()
58 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0}; in mlx5_query_vport_state()
68 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0}; in mlx5_query_vport_admin_state()
79 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {0}; in mlx5_modify_vport_admin_state()
80 u32 out[MLX5_ST_SZ_DW(modify_vport_state_out)] = {0}; in mlx5_modify_vport_admin_state()
104 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; in mlx5_query_nic_vport_context()
134 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; in mlx5_vport_alloc_q_counter()
135 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; in mlx5_vport_alloc_q_counter()
159 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {0}; in mlx5_vport_dealloc_q_counter()
160 u32 out[MLX5_ST_SZ_DW(dealloc_q_counter_out)] = {0}; in mlx5_vport_dealloc_q_counter()
[all …]
Dmlx5_uar.c36 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0}; in mlx5_cmd_alloc_uar()
37 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0}; in mlx5_cmd_alloc_uar()
54 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0}; in mlx5_cmd_free_uar()
55 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0}; in mlx5_cmd_free_uar()
Dmlx5_srq.c285 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd()
317 u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0}; in destroy_srq_cmd()
318 u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0}; in destroy_srq_cmd()
329 u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0}; in query_srq_cmd()
358 u32 srq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0}; in arm_srq_cmd()
359 u32 srq_out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0}; in arm_srq_cmd()
Dmlx5_rl.c61 u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {}; in mlx5_set_rate_limit_cmd()
62 u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {}; in mlx5_set_rate_limit_cmd()
Dmlx5_main.c218 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; in mlx5_pci_read_power_status()
219 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; in mlx5_pci_read_power_status()
417 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; in set_caps()
530 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; in mlx5_core_enable_hca()
531 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; in mlx5_core_enable_hca()
540 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; in mlx5_core_disable_hca()
541 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; in mlx5_core_disable_hca()
549 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; in mlx5_core_set_issi()
550 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; in mlx5_core_set_issi()
574 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; in mlx5_core_set_issi()
[all …]
Dmlx5_eq.c91 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; in mlx5_cmd_destroy_eq()
92 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; in mlx5_cmd_destroy_eq()
424 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; in mlx5_create_map_eq()
632 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; in mlx5_core_eq_query()
Dmlx5_pagealloc.c299 u32 in[MLX5_ST_SZ_DW(query_pages_in)] = {0}; in mlx5_cmd_query_pages()
300 u32 out[MLX5_ST_SZ_DW(query_pages_out)] = {0}; in mlx5_cmd_query_pages()
321 u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0}; in give_pages()
419 u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0}; in reclaim_pages()
Dflow_table.h39 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
Dmlx5_eswitch.c90 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0}; in arm_vport_context_events_cmd()
91 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0}; in arm_vport_context_events_cmd()
119 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0}; in query_esw_vport_context_cmd()
134 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0}; in query_esw_vport_cvlan()
172 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0}; in modify_esw_vport_context_cmd()
187 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0}; in modify_esw_vport_cvlan()
/freebsd-12-stable/sys/dev/mlx5/mlx5_fpga/
Dmlx5fpga_cmd.c42 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
77 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
86 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
87 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
130 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_write()
131 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_write()
153 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
154 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
171 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_connect()
172 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_connect()
[all …]
Dconn.h52 u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
/freebsd-12-stable/sys/dev/mlx5/
Dfs.h73 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
74 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
210 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
211 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
217 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
/freebsd-12-stable/sys/dev/mlx5/mlx5_lib/
Dmlx5_gid.c128 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; in mlx5_core_roce_gid_set()
129 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; in mlx5_core_roce_gid_set()
/freebsd-12-stable/sys/dev/mlx5/mlx5_fpga_tools/
Dmlx5fpga_tools_char.c194 CTASSERT(MLX5_FPGA_CAP_ARR_SZ == MLX5_ST_SZ_DW(fpga_cap));
205 u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in tools_char_ioctl()
/freebsd-12-stable/sys/dev/mlx5/mlx5_en/
Dmlx5_en_ethtool.c352 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_update()
422 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_mask_10x_25x_handler()
423 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_mask_10x_25x_handler()
527 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_mask_50x_handler()
528 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_mask_50x_handler()
827 u32 out_cap[MLX5_ST_SZ_DW(mtcap)] = {}; in mlx5e_hw_temperature_update()
845 u32 out_sensor[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5e_hw_temperature_update()

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