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Searched refs:MLX5_CAP_GEN (Results 1 – 25 of 32) sorted by relevance

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/freebsd-12-stable/sys/dev/mlx5/mlx5_core/
Dmlx5_fw.c142 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { in mlx5_query_hca_caps()
148 if (MLX5_CAP_GEN(dev, pg)) { in mlx5_query_hca_caps()
154 if (MLX5_CAP_GEN(dev, atomic)) { in mlx5_query_hca_caps()
160 if (MLX5_CAP_GEN(dev, roce)) { in mlx5_query_hca_caps()
166 if ((MLX5_CAP_GEN(dev, port_type) == in mlx5_query_hca_caps()
168 MLX5_CAP_GEN(dev, nic_flow_table)) || in mlx5_query_hca_caps()
169 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB && in mlx5_query_hca_caps()
170 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) { in mlx5_query_hca_caps()
176 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) { in mlx5_query_hca_caps()
182 if (MLX5_CAP_GEN(dev, vport_group_manager)) { in mlx5_query_hca_caps()
[all …]
Dmlx5_diagnostics.c94 if (MLX5_CAP_GEN(dev, debug) == 0) in mlx5_core_set_diagnostics_full()
97 numcounters = MLX5_CAP_GEN(dev, num_of_diagnostic_counters); in mlx5_core_set_diagnostics_full()
175 if (MLX5_CAP_GEN(dev, debug) == 0) in mlx5_core_get_diagnostics_full()
178 numcounters = MLX5_CAP_GEN(dev, num_of_diagnostic_counters); in mlx5_core_get_diagnostics_full()
273 if (MLX5_CAP_GEN(dev, debug) == 0) in mlx5_core_supports_diagnostics()
280 numcounters = MLX5_CAP_GEN(dev, num_of_diagnostic_counters); in mlx5_core_supports_diagnostics()
Dmlx5_vport.c121 return (MLX5_CAP_GEN(mdev, max_qp_cnt) - in mlx5_vport_max_q_counter_allocator()
517 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5_modify_nic_vport_node_guid()
556 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5_modify_nic_vport_port_guid()
788 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list) : in mlx5_modify_nic_vport_mac_list()
789 1 << MLX5_CAP_GEN(dev, log_max_current_mc_list); in mlx5_modify_nic_vport_mac_list()
842 max_list_size = 1 << MLX5_CAP_GEN(dev, log_max_vlan_list); in mlx5_query_nic_vport_vlans()
899 max_list_size = 1 << MLX5_CAP_GEN(dev, log_max_vlan_list); in mlx5_modify_nic_vport_vlans()
1013 is_group_manager = MLX5_CAP_GEN(dev, vport_group_manager); in mlx5_core_query_vport_counter()
1031 if (MLX5_CAP_GEN(dev, num_ports) == 2) in mlx5_core_query_vport_counter()
1048 is_group_manager = MLX5_CAP_GEN(mdev, vport_group_manager); in mlx5_query_hca_vport_context()
[all …]
Dmlx5_mpfs.c45 const u32 l2table_size = MIN(1U << MLX5_CAP_GEN(dev, log_max_l2_table), in mlx5_mpfs_add_mac()
53 if (!MLX5_CAP_GEN(dev, eswitch_flow_table)) { in mlx5_mpfs_add_mac()
93 if (!MLX5_CAP_GEN(dev, eswitch_flow_table)) { in mlx5_mpfs_del_mac()
Dmlx5_eq.c547 if (MLX5_CAP_GEN(dev, port_module_event)) in mlx5_start_eqs()
551 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) in mlx5_start_eqs()
555 if (MLX5_CAP_GEN(dev, dcbx)) in mlx5_start_eqs()
559 if (MLX5_CAP_GEN(dev, fpga)) in mlx5_start_eqs()
563 if (MLX5_CAP_GEN(dev, temp_warn_event)) in mlx5_start_eqs()
566 if (MLX5_CAP_GEN(dev, general_notification_event)) { in mlx5_start_eqs()
Dmlx5_eswitch.c1028 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || in mlx5_eswitch_enable_sriov()
1029 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_eswitch_enable_sriov()
1032 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) || in mlx5_eswitch_enable_sriov()
1068 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || in mlx5_eswitch_disable_sriov()
1069 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_eswitch_disable_sriov()
1086 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table); in mlx5_eswitch_init()
1091 if (!MLX5_CAP_GEN(dev, vport_group_manager) || in mlx5_eswitch_init()
1092 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_eswitch_init()
1157 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || in mlx5_eswitch_cleanup()
1158 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_eswitch_cleanup()
[all …]
Deswitch.h35 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
38 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
Dmlx5_port.c455 if (MLX5_CAP_GEN(dev, wol_s)) in mlx5_is_wol_supported()
457 if (MLX5_CAP_GEN(dev, wol_g)) in mlx5_is_wol_supported()
459 if (MLX5_CAP_GEN(dev, wol_a)) in mlx5_is_wol_supported()
461 if (MLX5_CAP_GEN(dev, wol_b)) in mlx5_is_wol_supported()
463 if (MLX5_CAP_GEN(dev, wol_m)) in mlx5_is_wol_supported()
465 if (MLX5_CAP_GEN(dev, wol_u)) in mlx5_is_wol_supported()
467 if (MLX5_CAP_GEN(dev, wol_p)) in mlx5_is_wol_supported()
843 if (!MLX5_CAP_GEN(mdev, ets)) in mlx5_query_port_qetcr_reg()
853 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8; in mlx5_max_tc()
864 if (!MLX5_CAP_GEN(mdev, ets)) in mlx5_set_port_qetcr_reg()
Dmlx5_uar.c115 bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2; in mlx5_alloc_uuars()
120 (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) + in mlx5_alloc_uuars()
Dmlx5_main.c284 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); in mlx5_enable_msix()
292 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); in mlx5_enable_msix()
444 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), in handle_hca_cap()
477 if (MLX5_CAP_GEN(dev, atomic)) { in handle_hca_cap_atomic()
516 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && in set_hca_ctrl()
517 !MLX5_CAP_GEN(dev, roce)) in set_hca_ctrl()
925 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) in mlx5_pci_close()
1614 if (MLX5_CAP_GEN(dev, vport_group_manager)) { in init_one()
1907 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); in mlx5_try_fast_unload()
1908 force_teardown = MLX5_CAP_GEN(dev, force_teardown); in mlx5_try_fast_unload()
Dmlx5_rl.c166 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) { in mlx5_init_rl_table()
Dmlx5_mr.c74 if (MLX5_CAP_GEN(dev, relaxed_ordering_write)) in mlx5_core_create_mkey_cb()
/freebsd-12-stable/sys/dev/mlx5/mlx5_ib/
Dmlx5_ib_main.c91 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); in mlx5_ib_port_link_layer()
319 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); in mlx5_query_port_roce()
471 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) in mlx5_use_mad_ifc()
472 return !MLX5_CAP_GEN(dev->mdev, ib_virt); in mlx5_use_mad_ifc()
560 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, in mlx5_query_max_pkeys()
643 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); in mlx5_ib_query_device()
679 if (MLX5_CAP_GEN(mdev, pkv)) in mlx5_ib_query_device()
681 if (MLX5_CAP_GEN(mdev, qkv)) in mlx5_ib_query_device()
683 if (MLX5_CAP_GEN(mdev, apm)) in mlx5_ib_query_device()
685 if (MLX5_CAP_GEN(mdev, xrc)) in mlx5_ib_query_device()
[all …]
Dmlx5_ib_qp.c239 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) in set_rq_size()
261 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { in set_rq_size()
264 MLX5_CAP_GEN(dev->mdev, in set_rq_size()
386 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in calc_sq_size()
388 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); in calc_sq_size()
401 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { in calc_sq_size()
404 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); in calc_sq_size()
427 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in set_user_buf_size()
429 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); in set_user_buf_size()
441 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { in set_user_buf_size()
[all …]
Dmlx5_ib_srq.c142 if (MLX5_CAP_GEN(dev->mdev, cqe_version) == MLX5_CQE_VERSION_V1 && in create_srq_user()
203 if (MLX5_CAP_GEN(dev->mdev, cqe_version) == MLX5_CQE_VERSION_V1 && in create_srq_kernel()
244 __u32 max_srq_wqes = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); in mlx5_ib_create_srq()
Dmlx5_ib_cq.c920 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) in mlx5_ib_create_cq()
927 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) in mlx5_ib_create_cq()
1103 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) in mlx5_ib_modify_cq()
1255 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { in mlx5_ib_resize_cq()
1261 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { in mlx5_ib_resize_cq()
1264 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); in mlx5_ib_resize_cq()
1269 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) in mlx5_ib_resize_cq()
Dmlx5_ib_mad.c248 if (MLX5_CAP_GEN(mdev, vport_counters) && in mlx5_ib_process_mad()
502 if (port < 1 || port > MLX5_CAP_GEN(mdev, num_ports)) { in mlx5_query_mad_ifc_port()
532 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); in mlx5_query_mad_ifc_port()
Dmlx5_ib_cong.c337 if (!MLX5_CAP_GEN(dev->mdev, cc_modify_allowed)) in mlx5_ib_cong_params_handler()
418 if (!MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) in mlx5_ib_init_congestion()
/freebsd-12-stable/sys/dev/mlx5/mlx5_en/
Dmlx5_en_ethtool.c152 if (MLX5_CAP_GEN(mdev, qcam_reg) == 0 || in mlx5e_get_dscp()
296 if (!MLX5_CAP_GEN(priv->mdev, ets)) { in mlx5e_get_prio_tc()
356 if (!MLX5_CAP_GEN(mdev, pcam_reg)) in mlx5e_fec_update()
441 if (!MLX5_CAP_GEN(mdev, pcam_reg)) { in mlx5e_fec_mask_10x_25x_handler()
546 if (!MLX5_CAP_GEN(mdev, pcam_reg)) { in mlx5e_fec_mask_50x_handler()
894 mode_modify = MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify); in mlx5e_ethtool_handler()
1140 MLX5_CAP_GEN(priv->mdev, cqe_compression)) { in mlx5e_ethtool_handler()
1213 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) { in mlx5e_ethtool_handler()
1225 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) { in mlx5e_ethtool_handler()
1415 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) { in mlx5e_create_ethtool()
Dport_buffer.h38 #define MLX5_BUFFER_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, pcam_reg) && \
Dmlx5_en_rl.c75 if (MLX5_CAP_GEN(rl->priv->mdev, cq_period_start_from_cqe)) in mlx5e_rl_build_cq_param()
745 if (!MLX5_CAP_GEN(priv->mdev, qos) || !MLX5_CAP_QOS(priv->mdev, packet_pacing)) in mlx5e_rl_init()
965 if (!MLX5_CAP_GEN(priv->mdev, qos) || !MLX5_CAP_QOS(priv->mdev, packet_pacing)) in mlx5e_rl_cleanup()
1112 if (!MLX5_CAP_GEN(priv->mdev, qos) || in mlx5e_rl_snd_tag_alloc()
1229 if (MLX5_CAP_GEN(rl->priv->mdev, cq_period_mode_modify)) { in mlx5e_rl_refresh_channel_params()
1370 mode_modify = MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify); in mlx5e_rl_sysctl_handler()
Dmlx5_en_main.c780 if (MLX5_CAP_GEN(mdev, pcam_reg) && in mlx5e_update_pport_counters()
820 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) in mlx5e_grp_vnic_env_update_stats()
1662 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; in mlx5e_create_sq()
2383 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) in mlx5e_build_rx_cq_param()
2398 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) in mlx5e_build_rx_cq_param()
2427 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) in mlx5e_build_tx_cq_param()
2498 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { in mlx5e_refresh_sq_params()
2526 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { in mlx5e_refresh_rq_params()
3562 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5e_check_required_hca_cap()
3574 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - in mlx5e_get_max_inline_cap()
[all …]
/freebsd-12-stable/sys/dev/mlx5/mlx5_lib/
Dmlx5_gid.c137 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_core_roce_gid_set()
/freebsd-12-stable/sys/dev/mlx5/mlx5_fpga/
Dmlx5fpga_ipsec.c82 if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga)) in mlx5_fpga_is_ipsec_device()
Dmlx5fpga_core.c337 if (!MLX5_CAP_GEN(mdev, fpga)) { in mlx5_fpga_init()

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