1 /*-
2 * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/12/sys/dev/mlx5/device.h 361412 2020-05-23 11:56:42Z kib $
26 */
27
28 #ifndef MLX5_DEVICE_H
29 #define MLX5_DEVICE_H
30
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
34
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
37 #define FW_PRE_INIT_TIMEOUT_MILI 120000
38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72 /* insert a value to a struct */
73 #define MLX5_SET(typ, p, fld, v) do { \
74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80 } while (0)
81
82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
88 << __mlx5_dw_bit_off(typ, fld))); \
89 } while (0)
90
91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
93 __mlx5_mask(typ, fld))
94
95 #define MLX5_GET_PR(typ, p, fld) ({ \
96 u32 ___t = MLX5_GET(typ, p, fld); \
97 pr_debug(#fld " = 0x%x\n", ___t); \
98 ___t; \
99 })
100
101 #define __MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
104 } while (0)
105
106 #define MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld, v); \
109 } while (0)
110
111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld[idx], v); \
114 } while (0)
115
116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
117
118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
120 __mlx5_mask16(typ, fld))
121
122 #define MLX5_SET16(typ, p, fld, v) do { \
123 u16 _v = v; \
124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
128 << __mlx5_16_bit_off(typ, fld))); \
129 } while (0)
130
131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
132 __mlx5_64_off(typ, fld)))
133
134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
135 type_t tmp; \
136 switch (sizeof(tmp)) { \
137 case sizeof(u8): \
138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
139 break; \
140 case sizeof(u16): \
141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
142 break; \
143 case sizeof(u32): \
144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
145 break; \
146 case sizeof(u64): \
147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
148 break; \
149 } \
150 tmp; \
151 })
152
153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
159
160 /* insert a value to a struct */
161 #define MLX5_VSC_SET(typ, p, fld, v) do { \
162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
167 << __mlx5_dw_bit_off(typ, fld))); \
168 } while (0)
169
170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
172 __mlx5_mask(typ, fld))
173
174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
176 pr_debug(#fld " = 0x%x\n", ___t); \
177 ___t; \
178 })
179
180 enum {
181 MLX5_MAX_COMMANDS = 32,
182 MLX5_CMD_DATA_BLOCK_SIZE = 512,
183 MLX5_CMD_MBOX_SIZE = 1024,
184 MLX5_PCI_CMD_XPORT = 7,
185 MLX5_MKEY_BSF_OCTO_SIZE = 4,
186 MLX5_MAX_PSVS = 4,
187 };
188
189 enum {
190 MLX5_EXTENDED_UD_AV = 0x80000000,
191 };
192
193 enum {
194 MLX5_CQ_FLAGS_OI = 2,
195 };
196
197 enum {
198 MLX5_STAT_RATE_OFFSET = 5,
199 };
200
201 enum {
202 MLX5_INLINE_SEG = 0x80000000,
203 };
204
205 enum {
206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
207 };
208
209 enum {
210 MLX5_MIN_PKEY_TABLE_SIZE = 128,
211 MLX5_MAX_LOG_PKEY_TABLE = 5,
212 };
213
214 enum {
215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
216 };
217
218 enum {
219 MLX5_PERM_LOCAL_READ = 1 << 2,
220 MLX5_PERM_LOCAL_WRITE = 1 << 3,
221 MLX5_PERM_REMOTE_READ = 1 << 4,
222 MLX5_PERM_REMOTE_WRITE = 1 << 5,
223 MLX5_PERM_ATOMIC = 1 << 6,
224 MLX5_PERM_UMR_EN = 1 << 7,
225 };
226
227 enum {
228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
233 };
234
235 enum {
236 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
238 MLX5_MKEY_BSF_EN = 1 << 30,
239 MLX5_MKEY_LEN64 = 1U << 31,
240 };
241
242 enum {
243 MLX5_EN_RD = (u64)1,
244 MLX5_EN_WR = (u64)2
245 };
246
247 enum {
248 MLX5_BF_REGS_PER_PAGE = 4,
249 MLX5_MAX_UAR_PAGES = 1 << 8,
250 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
251 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
252 };
253
254 enum {
255 MLX5_MKEY_MASK_LEN = 1ull << 0,
256 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
257 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
258 MLX5_MKEY_MASK_PD = 1ull << 7,
259 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
260 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
261 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
262 MLX5_MKEY_MASK_KEY = 1ull << 13,
263 MLX5_MKEY_MASK_QPN = 1ull << 14,
264 MLX5_MKEY_MASK_LR = 1ull << 17,
265 MLX5_MKEY_MASK_LW = 1ull << 18,
266 MLX5_MKEY_MASK_RR = 1ull << 19,
267 MLX5_MKEY_MASK_RW = 1ull << 20,
268 MLX5_MKEY_MASK_A = 1ull << 21,
269 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
270 MLX5_MKEY_MASK_FREE = 1ull << 29,
271 };
272
273 enum {
274 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
275
276 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
277 MLX5_UMR_CHECK_FREE = (2 << 5),
278
279 MLX5_UMR_INLINE = (1 << 7),
280 };
281
282 #define MLX5_UMR_MTT_ALIGNMENT 0x40
283 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
284 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
285
286 enum {
287 MLX5_EVENT_QUEUE_TYPE_QP = 0,
288 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
289 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
290 };
291
292 enum {
293 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
294 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
295 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
296 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
297 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
298 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
299 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
300 };
301
302 enum {
303 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
305 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
306 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
307 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
308 };
309
310 enum {
311 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
312 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
313 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
314 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
315 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
316 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
317 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
318 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
319 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
320 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
321 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
322 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
323 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
324 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
325 };
326
327 enum {
328 MLX5_ROCE_VERSION_1 = 0,
329 MLX5_ROCE_VERSION_1_5 = 1,
330 MLX5_ROCE_VERSION_2 = 2,
331 };
332
333 enum {
334 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
335 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
336 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
337 };
338
339 enum {
340 MLX5_ROCE_L3_TYPE_IPV4 = 0,
341 MLX5_ROCE_L3_TYPE_IPV6 = 1,
342 };
343
344 enum {
345 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
346 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
347 };
348
349 enum {
350 MLX5_OPCODE_NOP = 0x00,
351 MLX5_OPCODE_SEND_INVAL = 0x01,
352 MLX5_OPCODE_RDMA_WRITE = 0x08,
353 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
354 MLX5_OPCODE_SEND = 0x0a,
355 MLX5_OPCODE_SEND_IMM = 0x0b,
356 MLX5_OPCODE_LSO = 0x0e,
357 MLX5_OPCODE_RDMA_READ = 0x10,
358 MLX5_OPCODE_ATOMIC_CS = 0x11,
359 MLX5_OPCODE_ATOMIC_FA = 0x12,
360 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
361 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
362 MLX5_OPCODE_BIND_MW = 0x18,
363 MLX5_OPCODE_CONFIG_CMD = 0x1f,
364
365 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
366 MLX5_RECV_OPCODE_SEND = 0x01,
367 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
368 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
369
370 MLX5_CQE_OPCODE_ERROR = 0x1e,
371 MLX5_CQE_OPCODE_RESIZE = 0x16,
372
373 MLX5_OPCODE_SET_PSV = 0x20,
374 MLX5_OPCODE_GET_PSV = 0x21,
375 MLX5_OPCODE_CHECK_PSV = 0x22,
376 MLX5_OPCODE_RGET_PSV = 0x26,
377 MLX5_OPCODE_RCHECK_PSV = 0x27,
378
379 MLX5_OPCODE_UMR = 0x25,
380
381 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
382 };
383
384 enum {
385 MLX5_SET_PORT_RESET_QKEY = 0,
386 MLX5_SET_PORT_GUID0 = 16,
387 MLX5_SET_PORT_NODE_GUID = 17,
388 MLX5_SET_PORT_SYS_GUID = 18,
389 MLX5_SET_PORT_GID_TABLE = 19,
390 MLX5_SET_PORT_PKEY_TABLE = 20,
391 };
392
393 enum {
394 MLX5_MAX_PAGE_SHIFT = 31
395 };
396
397 enum {
398 MLX5_ADAPTER_PAGE_SHIFT = 12,
399 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
400 };
401
402 enum {
403 MLX5_CAP_OFF_CMDIF_CSUM = 46,
404 };
405
406 enum {
407 /*
408 * Max wqe size for rdma read is 512 bytes, so this
409 * limits our max_sge_rd as the wqe needs to fit:
410 * - ctrl segment (16 bytes)
411 * - rdma segment (16 bytes)
412 * - scatter elements (16 bytes each)
413 */
414 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
415 };
416
417 struct mlx5_cmd_layout {
418 u8 type;
419 u8 rsvd0[3];
420 __be32 inlen;
421 __be64 in_ptr;
422 __be32 in[4];
423 __be32 out[4];
424 __be64 out_ptr;
425 __be32 outlen;
426 u8 token;
427 u8 sig;
428 u8 rsvd1;
429 u8 status_own;
430 };
431
432 enum mlx5_fatal_assert_bit_offsets {
433 MLX5_RFR_OFFSET = 31,
434 };
435
436 struct mlx5_health_buffer {
437 __be32 assert_var[5];
438 __be32 rsvd0[3];
439 __be32 assert_exit_ptr;
440 __be32 assert_callra;
441 __be32 rsvd1[2];
442 __be32 fw_ver;
443 __be32 hw_id;
444 __be32 rfr;
445 u8 irisc_index;
446 u8 synd;
447 __be16 ext_synd;
448 };
449
450 enum mlx5_initializing_bit_offsets {
451 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
452 };
453
454 enum mlx5_cmd_addr_l_sz_offset {
455 MLX5_NIC_IFC_OFFSET = 8,
456 };
457
458 struct mlx5_init_seg {
459 __be32 fw_rev;
460 __be32 cmdif_rev_fw_sub;
461 __be32 rsvd0[2];
462 __be32 cmdq_addr_h;
463 __be32 cmdq_addr_l_sz;
464 __be32 cmd_dbell;
465 __be32 rsvd1[120];
466 __be32 initializing;
467 struct mlx5_health_buffer health;
468 __be32 rsvd2[880];
469 __be32 internal_timer_h;
470 __be32 internal_timer_l;
471 __be32 rsvd3[2];
472 __be32 health_counter;
473 __be32 rsvd4[1019];
474 __be64 ieee1588_clk;
475 __be32 ieee1588_clk_type;
476 __be32 clr_intx;
477 };
478
479 struct mlx5_eqe_comp {
480 __be32 reserved[6];
481 __be32 cqn;
482 };
483
484 struct mlx5_eqe_qp_srq {
485 __be32 reserved[6];
486 __be32 qp_srq_n;
487 };
488
489 struct mlx5_eqe_cq_err {
490 __be32 cqn;
491 u8 reserved1[7];
492 u8 syndrome;
493 };
494
495 struct mlx5_eqe_port_state {
496 u8 reserved0[8];
497 u8 port;
498 };
499
500 struct mlx5_eqe_gpio {
501 __be32 reserved0[2];
502 __be64 gpio_event;
503 };
504
505 struct mlx5_eqe_congestion {
506 u8 type;
507 u8 rsvd0;
508 u8 congestion_level;
509 };
510
511 struct mlx5_eqe_stall_vl {
512 u8 rsvd0[3];
513 u8 port_vl;
514 };
515
516 struct mlx5_eqe_cmd {
517 __be32 vector;
518 __be32 rsvd[6];
519 };
520
521 struct mlx5_eqe_page_req {
522 u8 rsvd0[2];
523 __be16 func_id;
524 __be32 num_pages;
525 __be32 rsvd1[5];
526 };
527
528 struct mlx5_eqe_vport_change {
529 u8 rsvd0[2];
530 __be16 vport_num;
531 __be32 rsvd1[6];
532 };
533
534
535 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
536 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
537
538 enum {
539 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
540 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
541 MLX5_MODULE_STATUS_ERROR = 0x3,
542 MLX5_MODULE_STATUS_NUM ,
543 };
544
545 enum {
546 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
547 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
548 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
549 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
550 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
551 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
552 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
553 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
554 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8,
555 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9,
556 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa,
557 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb,
558 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc,
559 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd,
560 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe,
561 MLX5_MODULE_EVENT_ERROR_NUM ,
562 };
563
564 struct mlx5_eqe_port_module_event {
565 u8 rsvd0;
566 u8 module;
567 u8 rsvd1;
568 u8 module_status;
569 u8 rsvd2[2];
570 u8 error_type;
571 };
572
573 struct mlx5_eqe_general_notification_event {
574 u32 rq_user_index_delay_drop;
575 u32 rsvd0[6];
576 };
577
578 struct mlx5_eqe_temp_warning {
579 __be64 sensor_warning_msb;
580 __be64 sensor_warning_lsb;
581 } __packed;
582
583 union ev_data {
584 __be32 raw[7];
585 struct mlx5_eqe_cmd cmd;
586 struct mlx5_eqe_comp comp;
587 struct mlx5_eqe_qp_srq qp_srq;
588 struct mlx5_eqe_cq_err cq_err;
589 struct mlx5_eqe_port_state port;
590 struct mlx5_eqe_gpio gpio;
591 struct mlx5_eqe_congestion cong;
592 struct mlx5_eqe_stall_vl stall_vl;
593 struct mlx5_eqe_page_req req_pages;
594 struct mlx5_eqe_port_module_event port_module_event;
595 struct mlx5_eqe_vport_change vport_change;
596 struct mlx5_eqe_general_notification_event general_notifications;
597 struct mlx5_eqe_temp_warning temp_warning;
598 } __packed;
599
600 struct mlx5_eqe {
601 u8 rsvd0;
602 u8 type;
603 u8 rsvd1;
604 u8 sub_type;
605 __be32 rsvd2[7];
606 union ev_data data;
607 __be16 rsvd3;
608 u8 signature;
609 u8 owner;
610 } __packed;
611
612 struct mlx5_cmd_prot_block {
613 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
614 u8 rsvd0[48];
615 __be64 next;
616 __be32 block_num;
617 u8 rsvd1;
618 u8 token;
619 u8 ctrl_sig;
620 u8 sig;
621 };
622
623 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
624 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
625 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
626 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
627
628 enum {
629 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
630 };
631
632 struct mlx5_err_cqe {
633 u8 rsvd0[32];
634 __be32 srqn;
635 u8 rsvd1[18];
636 u8 vendor_err_synd;
637 u8 syndrome;
638 __be32 s_wqe_opcode_qpn;
639 __be16 wqe_counter;
640 u8 signature;
641 u8 op_own;
642 };
643
644 struct mlx5_cqe64 {
645 u8 tunneled_etc;
646 u8 rsvd0[3];
647 u8 lro_tcppsh_abort_dupack;
648 u8 lro_min_ttl;
649 __be16 lro_tcp_win;
650 __be32 lro_ack_seq_num;
651 __be32 rss_hash_result;
652 u8 rss_hash_type;
653 u8 ml_path;
654 u8 rsvd20[2];
655 __be16 check_sum;
656 __be16 slid;
657 __be32 flags_rqpn;
658 u8 hds_ip_ext;
659 u8 l4_hdr_type_etc;
660 __be16 vlan_info;
661 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
662 __be32 imm_inval_pkey;
663 u8 rsvd40[4];
664 __be32 byte_cnt;
665 __be64 timestamp;
666 __be32 sop_drop_qpn;
667 __be16 wqe_counter;
668 u8 signature;
669 u8 op_own;
670 };
671
672 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
673
get_cqe_lro_timestamp_valid(struct mlx5_cqe64 * cqe)674 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
675 {
676 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
677 }
678
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)679 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
680 {
681 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
682 }
683
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)684 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
685 {
686 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
687 }
688
get_cqe_vlan(struct mlx5_cqe64 * cqe)689 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
690 {
691 return be16_to_cpu(cqe->vlan_info) & 0xfff;
692 }
693
get_cqe_smac(struct mlx5_cqe64 * cqe,u8 * smac)694 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
695 {
696 memcpy(smac, &cqe->rss_hash_type , 4);
697 memcpy(smac + 4, &cqe->slid , 2);
698 }
699
cqe_has_vlan(struct mlx5_cqe64 * cqe)700 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
701 {
702 return cqe->l4_hdr_type_etc & 0x1;
703 }
704
cqe_is_tunneled(struct mlx5_cqe64 * cqe)705 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
706 {
707 return cqe->tunneled_etc & 0x1;
708 }
709
710 enum {
711 CQE_L4_HDR_TYPE_NONE = 0x0,
712 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
713 CQE_L4_HDR_TYPE_UDP = 0x2,
714 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
715 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
716 };
717
718 enum {
719 /* source L3 hash types */
720 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
721 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
722 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
723
724 /* destination L3 hash types */
725 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
726 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
727 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
728
729 /* source L4 hash types */
730 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
731 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
732 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
733 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
734
735 /* destination L4 hash types */
736 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
737 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
738 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
739 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
740 };
741
742 enum {
743 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
744 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
745 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
746 };
747
748 enum {
749 CQE_L2_OK = 1 << 0,
750 CQE_L3_OK = 1 << 1,
751 CQE_L4_OK = 1 << 2,
752 };
753
754 struct mlx5_sig_err_cqe {
755 u8 rsvd0[16];
756 __be32 expected_trans_sig;
757 __be32 actual_trans_sig;
758 __be32 expected_reftag;
759 __be32 actual_reftag;
760 __be16 syndrome;
761 u8 rsvd22[2];
762 __be32 mkey;
763 __be64 err_offset;
764 u8 rsvd30[8];
765 __be32 qpn;
766 u8 rsvd38[2];
767 u8 signature;
768 u8 op_own;
769 };
770
771 struct mlx5_wqe_srq_next_seg {
772 u8 rsvd0[2];
773 __be16 next_wqe_index;
774 u8 signature;
775 u8 rsvd1[11];
776 };
777
778 union mlx5_ext_cqe {
779 struct ib_grh grh;
780 u8 inl[64];
781 };
782
783 struct mlx5_cqe128 {
784 union mlx5_ext_cqe inl_grh;
785 struct mlx5_cqe64 cqe64;
786 };
787
788 enum {
789 MLX5_MKEY_STATUS_FREE = 1 << 6,
790 };
791
792 struct mlx5_mkey_seg {
793 /* This is a two bit field occupying bits 31-30.
794 * bit 31 is always 0,
795 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
796 */
797 u8 status;
798 u8 pcie_control;
799 u8 flags;
800 u8 version;
801 __be32 qpn_mkey7_0;
802 u8 rsvd1[4];
803 __be32 flags_pd;
804 __be64 start_addr;
805 __be64 len;
806 __be32 bsfs_octo_size;
807 u8 rsvd2[16];
808 __be32 xlt_oct_size;
809 u8 rsvd3[3];
810 u8 log2_page_size;
811 u8 rsvd4[4];
812 };
813
814 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
815
816 enum {
817 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
818 };
819
mlx5_host_is_le(void)820 static inline int mlx5_host_is_le(void)
821 {
822 #if defined(__LITTLE_ENDIAN)
823 return 1;
824 #elif defined(__BIG_ENDIAN)
825 return 0;
826 #else
827 #error Host endianness not defined
828 #endif
829 }
830
831 #define MLX5_CMD_OP_MAX 0x939
832
833 enum {
834 VPORT_STATE_DOWN = 0x0,
835 VPORT_STATE_UP = 0x1,
836 VPORT_STATE_FOLLOW = 0x2,
837 };
838
839 enum {
840 MLX5_L3_PROT_TYPE_IPV4 = 0,
841 MLX5_L3_PROT_TYPE_IPV6 = 1,
842 };
843
844 enum {
845 MLX5_L4_PROT_TYPE_TCP = 0,
846 MLX5_L4_PROT_TYPE_UDP = 1,
847 };
848
849 enum {
850 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
851 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
852 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
853 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
854 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
855 };
856
857 enum {
858 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
859 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
860 MLX5_MATCH_INNER_HEADERS = 1 << 2,
861
862 };
863
864 enum {
865 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
866 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
867 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
868 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
869 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
870 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
871 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
872 };
873
874 enum {
875 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
876 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
877 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
878 };
879
880 enum {
881 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
882 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
883 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
884 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
885 };
886
887 enum {
888 MLX5_UC_ADDR_CHANGE = (1 << 0),
889 MLX5_MC_ADDR_CHANGE = (1 << 1),
890 MLX5_VLAN_CHANGE = (1 << 2),
891 MLX5_PROMISC_CHANGE = (1 << 3),
892 MLX5_MTU_CHANGE = (1 << 4),
893 };
894
895 enum mlx5_list_type {
896 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
897 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
898 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
899 };
900
901 enum {
902 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
903 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
904 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
905 };
906
907 /* MLX5 DEV CAPs */
908
909 /* TODO: EAT.ME */
910 enum mlx5_cap_mode {
911 HCA_CAP_OPMOD_GET_MAX = 0,
912 HCA_CAP_OPMOD_GET_CUR = 1,
913 };
914
915 enum mlx5_cap_type {
916 MLX5_CAP_GENERAL = 0,
917 MLX5_CAP_ETHERNET_OFFLOADS,
918 MLX5_CAP_ODP,
919 MLX5_CAP_ATOMIC,
920 MLX5_CAP_ROCE,
921 MLX5_CAP_IPOIB_OFFLOADS,
922 MLX5_CAP_EOIB_OFFLOADS,
923 MLX5_CAP_FLOW_TABLE,
924 MLX5_CAP_ESWITCH_FLOW_TABLE,
925 MLX5_CAP_ESWITCH,
926 MLX5_CAP_SNAPSHOT,
927 MLX5_CAP_VECTOR_CALC,
928 MLX5_CAP_QOS,
929 MLX5_CAP_DEBUG,
930 /* NUM OF CAP Types */
931 MLX5_CAP_NUM
932 };
933
934 enum mlx5_qcam_reg_groups {
935 MLX5_QCAM_REGS_FIRST_128 = 0x0,
936 };
937
938 enum mlx5_qcam_feature_groups {
939 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
940 };
941
942 enum mlx5_pcam_reg_groups {
943 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
944 };
945
946 enum mlx5_pcam_feature_groups {
947 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
948 };
949
950 enum mlx5_mcam_reg_groups {
951 MLX5_MCAM_REGS_FIRST_128 = 0x0,
952 };
953
954 enum mlx5_mcam_feature_groups {
955 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
956 };
957
958 /* GET Dev Caps macros */
959 #define MLX5_CAP_GEN(mdev, cap) \
960 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
961
962 #define MLX5_CAP_GEN_MAX(mdev, cap) \
963 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
964
965 #define MLX5_CAP_ETH(mdev, cap) \
966 MLX5_GET(per_protocol_networking_offload_caps,\
967 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
968
969 #define MLX5_CAP_ETH_MAX(mdev, cap) \
970 MLX5_GET(per_protocol_networking_offload_caps,\
971 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
972
973 #define MLX5_CAP_ROCE(mdev, cap) \
974 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
975
976 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
977 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
978
979 #define MLX5_CAP_ATOMIC(mdev, cap) \
980 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
981
982 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
983 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
984
985 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
986 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
987
988 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
989 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
990
991 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
992 MLX5_GET(flow_table_eswitch_cap, \
993 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
994
995 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
996 MLX5_GET(flow_table_eswitch_cap, \
997 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
998
999 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1000 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1001
1002 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1003 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1004
1005 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1006 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1007
1008 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1009 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1010
1011 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1012 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1013
1014 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1015 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1016
1017 #define MLX5_CAP_ESW(mdev, cap) \
1018 MLX5_GET(e_switch_cap, \
1019 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1020
1021 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1022 MLX5_GET(e_switch_cap, \
1023 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1024
1025 #define MLX5_CAP_ODP(mdev, cap)\
1026 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1027
1028 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1029 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1030
1031 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1032 MLX5_GET(snapshot_cap, \
1033 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1034
1035 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1036 MLX5_GET(snapshot_cap, \
1037 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1038
1039 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1040 MLX5_GET(per_protocol_networking_offload_caps,\
1041 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1042
1043 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1044 MLX5_GET(per_protocol_networking_offload_caps,\
1045 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1046
1047 #define MLX5_CAP_DEBUG(mdev, cap) \
1048 MLX5_GET(debug_cap, \
1049 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1050
1051 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1052 MLX5_GET(debug_cap, \
1053 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1054
1055 #define MLX5_CAP_QOS(mdev, cap) \
1056 MLX5_GET(qos_cap,\
1057 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1058
1059 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1060 MLX5_GET(qos_cap,\
1061 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1062
1063 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1064 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1065
1066 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1067 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1068
1069 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1070 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1071
1072 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1073 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1074
1075 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1076 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1077
1078 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1079 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1080
1081 #define MLX5_CAP_FPGA(mdev, cap) \
1082 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1083
1084 #define MLX5_CAP64_FPGA(mdev, cap) \
1085 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1086
1087 enum {
1088 MLX5_CMD_STAT_OK = 0x0,
1089 MLX5_CMD_STAT_INT_ERR = 0x1,
1090 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1091 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1092 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1093 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1094 MLX5_CMD_STAT_RES_BUSY = 0x6,
1095 MLX5_CMD_STAT_LIM_ERR = 0x8,
1096 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1097 MLX5_CMD_STAT_IX_ERR = 0xa,
1098 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1099 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1100 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1101 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1102 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1103 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1104 };
1105
1106 enum {
1107 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1108 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1109 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1110 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1111 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1112 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1113 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1114 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1115 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1116 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1117 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1118 };
1119
1120 enum {
1121 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1122 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1123 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1124 };
1125
1126 enum {
1127 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE,
1128 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE,
1129 };
1130
1131 enum {
1132 NUM_DRIVER_UARS = 4,
1133 NUM_LOW_LAT_UUARS = 4,
1134 };
1135
1136 enum {
1137 MLX5_CAP_PORT_TYPE_IB = 0x0,
1138 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1139 };
1140
1141 enum {
1142 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1143 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1144 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1145 };
1146
1147 enum mlx5_inline_modes {
1148 MLX5_INLINE_MODE_NONE,
1149 MLX5_INLINE_MODE_L2,
1150 MLX5_INLINE_MODE_IP,
1151 MLX5_INLINE_MODE_TCP_UDP,
1152 };
1153
1154 enum {
1155 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1156 };
1157
mlx5_to_sw_pkey_sz(int pkey_sz)1158 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1159 {
1160 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1161 return 0;
1162 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1163 }
1164
1165 struct mlx5_ifc_mcia_reg_bits {
1166 u8 l[0x1];
1167 u8 reserved_0[0x7];
1168 u8 module[0x8];
1169 u8 reserved_1[0x8];
1170 u8 status[0x8];
1171
1172 u8 i2c_device_address[0x8];
1173 u8 page_number[0x8];
1174 u8 device_address[0x10];
1175
1176 u8 reserved_2[0x10];
1177 u8 size[0x10];
1178
1179 u8 reserved_3[0x20];
1180
1181 u8 dword_0[0x20];
1182 u8 dword_1[0x20];
1183 u8 dword_2[0x20];
1184 u8 dword_3[0x20];
1185 u8 dword_4[0x20];
1186 u8 dword_5[0x20];
1187 u8 dword_6[0x20];
1188 u8 dword_7[0x20];
1189 u8 dword_8[0x20];
1190 u8 dword_9[0x20];
1191 u8 dword_10[0x20];
1192 u8 dword_11[0x20];
1193 };
1194
1195 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1196
1197 struct mlx5_mini_cqe8 {
1198 union {
1199 __be32 rx_hash_result;
1200 __be16 checksum;
1201 __be16 rsvd;
1202 struct {
1203 __be16 wqe_counter;
1204 u8 s_wqe_opcode;
1205 u8 reserved;
1206 } s_wqe_info;
1207 };
1208 __be32 byte_cnt;
1209 };
1210
1211 enum {
1212 MLX5_NO_INLINE_DATA,
1213 MLX5_INLINE_DATA32_SEG,
1214 MLX5_INLINE_DATA64_SEG,
1215 MLX5_COMPRESSED,
1216 };
1217
1218 enum mlx5_exp_cqe_zip_recv_type {
1219 MLX5_CQE_FORMAT_HASH,
1220 MLX5_CQE_FORMAT_CSUM,
1221 };
1222
1223 #define MLX5E_CQE_FORMAT_MASK 0xc
mlx5_get_cqe_format(const struct mlx5_cqe64 * cqe)1224 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1225 {
1226 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1227 }
1228
1229 enum {
1230 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1231 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
1232 };
1233
1234 enum {
1235 MLX5_FRL_LEVEL3 = 0x8,
1236 MLX5_FRL_LEVEL6 = 0x40,
1237 };
1238
1239 /* 8 regular priorities + 1 for multicast */
1240 #define MLX5_NUM_BYPASS_FTS 9
1241
1242 #endif /* MLX5_DEVICE_H */
1243