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Searched refs:MCPhysReg (Results 1 – 25 of 181) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.h158 using llvm::MCPhysReg;
161 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
162 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
163 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
164 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
165 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
166 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
167 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
168 static const MCPhysReg RRegsNoR0[32] = \
170 static const MCPhysReg XRegsNoX0[32] = \
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DCallingConvLower.h168 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
171 MCPhysReg PReg;
336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
343 void DeallocateReg(MCPhysReg Reg) { in DeallocateReg()
351 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
359 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
376 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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DLivePhysRegs.h50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
79 void addReg(MCPhysReg Reg) { in addReg()
89 void removeReg(MCPhysReg Reg) { in removeReg()
98 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); } in contains()
109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
129 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order;
41 operator ArrayRef<MCPhysReg>() const {
59 const MCPhysReg *CalleeSavedRegs = nullptr;
62 SmallVector<MCPhysReg, 4> CalleeSavedAliases;
99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
DLiveRegUnits.h86 void addReg(MCPhysReg Reg) { in addReg()
93 void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) { in addRegMasked()
102 void removeReg(MCPhysReg Reg) { in removeReg()
116 bool available(MCPhysReg Reg) const { in available()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DRegAllocFast.cpp101 MCPhysReg PhysReg = 0; ///< Currently held here.
119 DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
163 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
164 bool isPhysRegFree(MCPhysReg PhysReg) const;
167 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
173 bool isClobberedByRegMasks(MCPhysReg PhysReg) const { in isClobberedByRegMasks()
180 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr()
194 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr()
200 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr()
251 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
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DAllocationOrder.h31 const SmallVector<MCPhysReg, 16> Hints;
32 ArrayRef<MCPhysReg> Order;
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
117 static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max())); in isHint()
DLivePhysRegs.cpp32 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers) { in removeRegsInMask() argument
81 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers) { in stepForward() argument
128 for (MCPhysReg R : *this) in print()
140 MCPhysReg Reg) const { in available()
155 MCPhysReg Reg = LI.PhysReg; in addBlockLiveIns()
175 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs()
203 for (MCPhysReg R : Pristine) in addPristines()
262 for (MCPhysReg Reg : LiveRegs) { in addLiveIns()
DRegisterClassInfo.cpp58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in runOnMachineFunction()
63 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
104 SmallVector<MCPhysReg, 16> CSRAlias; in compute()
111 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
159 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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DARMBaseRegisterInfo.h93 const MCPhysReg *CSRegs) { in isCalleeSavedRegister()
115 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
116 const MCPhysReg *
135 ArrayRef<MCPhysReg>
157 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
158 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/
DMCRegisterInfo.h33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const MCPhysReg *DiffLists; // Pointer to the difflists array
198 const MCPhysReg *List = nullptr;
207 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
217 MCPhysReg D = *List++; in advance()
243 std::forward_iterator_tag, MCPhysReg> {
246 MCPhysReg Val;
252 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
144 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.h61 virtual const MCPhysReg *
85 const MCPhysReg *
107 const MCPhysReg *
136 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
137 SmallVectorImpl<MCPhysReg> &Hints,
148 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
DSystemZCallingConv.cpp14 const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = {
18 const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] = {
23 const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = {
28 const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = {
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
DRegisterFile.h42 MCPhysReg RegisterID;
59 MCPhysReg getRegisterID() const;
167 MCPhysReg RenameAs;
168 MCPhysReg AliasRegID;
240 MCPhysReg RegisterID;
290 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/
DInstruction.h144 MCPhysReg RegisterID;
172 MCPhysReg RegisterID;
187 MCPhysReg RegID;
208 MCPhysReg RegisterID;
248 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
260 MCPhysReg getRegisterID() const { return RegisterID; } in getRegisterID()
261 void setRegisterID(const MCPhysReg RegID) { RegisterID = RegID; } in setRegisterID()
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
329 MCPhysReg RegisterID;
356 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
67 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) { in CC_X86_VectorCallGetSSEs()
69 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2, in CC_X86_VectorCallGetSSEs()
75 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2, in CC_X86_VectorCallGetSSEs()
80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
85 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() { in CC_X86_64_VectorCallGetGPRs()
86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
DX86RegisterInfo.h100 const MCPhysReg *
102 const MCPhysReg *
148 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
149 SmallVectorImpl<MCPhysReg> &Hints,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64CallingConvention.cpp23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
38 static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
132 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
DAArch64RedundantCopyElimination.cpp88 MCPhysReg Reg;
90 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {} in RegImm()
186 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
187 MCPhysReg SrcReg = PredI.getOperand(1).getReg(); in knownRegValInBlock()
252 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock()
325 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg(); in optimizeBlock()
405 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock()
459 for (MCPhysReg KnownReg : UsedKnownRegs) in optimizeBlock()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp66 const MCPhysReg *
71 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
74 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
77 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
80 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
85 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
88 static const MCPhysReg VecPred[] = { in getCallerSavedRegs()
109 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
118 const MCPhysReg *
120 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h67 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
68 const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
330 MCPhysReg get32BitRegister(MCPhysReg Reg) const;
338 ArrayRef<MCPhysReg> getAllSGPR128(const MachineFunction &MF) const;
342 ArrayRef<MCPhysReg> getAllSGPR64(const MachineFunction &MF) const;
346 ArrayRef<MCPhysReg> getAllSGPR32(const MachineFunction &MF) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
DRegisterFile.cpp58 MCPhysReg WriteRef::getRegisterID() const { in getRegisterID()
111 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted()
122 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in onInstructionExecuted()
170 for (const MCPhysReg Reg : RC) { in addRegisterFile()
231 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite()
282 MCPhysReg ZeroRegisterID = in addRegisterWrite()
326 MCPhysReg RegID = WS.getRegisterID(); in removeRegisterWrite()
338 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in removeRegisterWrite()
453 MCPhysReg AliasedReg = in tryEliminateMoveOrSwap()
455 MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID(); in tryEliminateMoveOrSwap()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp37 const MCPhysReg*
41 static const MCPhysReg CalleeSavedRegs[] = { in getCalleeSavedRegs()
46 static const MCPhysReg CalleeSavedRegsFP[] = { in getCalleeSavedRegs()
51 static const MCPhysReg CalleeSavedRegsIntr[] = { in getCalleeSavedRegs()
57 static const MCPhysReg CalleeSavedRegsIntrFP[] = { in getCalleeSavedRegs()

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