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Searched refs:MADD (Results 1 – 16 of 16) sorted by relevance

/freebsd-12-stable/contrib/bearssl/src/ec/
Dec_prime_i15.c153 #define MADD(d, a) (0x1000 + ((d) << 8) + ((a) << 4)) macro
225 MADD(t1, Px),
232 MADD(t1, t3),
233 MADD(t1, t3),
239 MADD(t3, t3),
241 MADD(t2, t2),
255 MADD(Pz, t4),
406 MADD(t1, P2y),
Dec_prime_i31.c151 #define MADD(d, a) (0x1000 + ((d) << 8) + ((a) << 4)) macro
223 MADD(t1, Px),
230 MADD(t1, t3),
231 MADD(t1, t3),
237 MADD(t3, t3),
239 MADD(t2, t2),
253 MADD(Pz, t4),
404 MADD(t1, P2y),
/freebsd-12-stable/contrib/gcc/config/mips/
D4k.md90 ;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
106 ;; 4Kp slow iterative MADD
107 ;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
115 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
D5k.md89 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
Dsr71k.md237 ;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
Dmips.md1196 ;; Splitter to copy result of MADD to a general register
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp1179 case CASE_VFMA_OPCODE_LMULS(MADD, VX): in findCommutedOpIndices()
1198 case CASE_VFMA_OPCODE_LMULS(MADD, VV): in findCommutedOpIndices()
1305 case CASE_VFMA_OPCODE_LMULS(MADD, VX): in commuteInstructionImpl()
1331 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX) in commuteInstructionImpl()
1332 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX) in commuteInstructionImpl()
1335 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV) in commuteInstructionImpl()
1348 case CASE_VFMA_OPCODE_LMULS(MADD, VV): in commuteInstructionImpl()
1362 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV) in commuteInstructionImpl()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DP9InstrResources.td403 (instregex "MADD(HD|HDU|LD|LD8)$"),
477 (instregex "F(N)?MADD(S)?_rec$"),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td201 def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
DMipsInstrInfo.td2380 // MADD*/MSUB*
2381 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2399 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
DMicroMipsInstrInfo.td1116 def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
DMipsScheduleGeneric.td147 def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td192 // MUL/MNEG are aliases for MADD/MSUB.
DAArch64InstrFormats.td2197 // MADD/MSUB generation is decided by MachineCombiner.cpp
DAArch64InstrInfo.td1623 defm MADD : MulAccum<0, "madd", add>;
/freebsd-12-stable/contrib/gcc/
DFSFChangeLog.113466 (GENERATE_{BRANCHLIKELY,MADD,MULT3): Likewise.