| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | ExpandMemCmp.cpp | 337 const LoadPair Loads = in emitLoadCompareByteBlock() local
340 Value *Diff = Builder.CreateSub(Loads.Lhs, Loads.Rhs); in emitLoadCompareByteBlock()
393 const LoadPair Loads = getLoadPair( in getCompareLoadPairs() local
400 Diff = Builder.CreateXor(Loads.Lhs, Loads.Rhs); in getCompareLoadPairs()
405 Cmp = Builder.CreateICmpNE(Loads.Lhs, Loads.Rhs); in getCompareLoadPairs()
486 const LoadPair Loads = in emitLoadCompareBlock() local
493 ResBlock.PhiSrc1->addIncoming(Loads.Lhs, LoadCmpBlocks[BlockIndex]); in emitLoadCompareBlock()
494 ResBlock.PhiSrc2->addIncoming(Loads.Rhs, LoadCmpBlocks[BlockIndex]); in emitLoadCompareBlock()
497 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_EQ, Loads.Lhs, Loads.Rhs); in emitLoadCompareBlock()
599 const LoadPair Loads = in getMemCmpOneBlock() local
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| D | ScheduleDAGInstrs.cpp | 761 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/); in buildSchedGraph() local
905 addBarrierChain(Loads); in buildSchedGraph()
949 addChainDependencies(SU, Loads); in buildSchedGraph()
963 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V); in buildSchedGraph()
976 addChainDependencies(SU, Loads, UnknownValue); in buildSchedGraph()
985 Loads.insert(SU, UnknownValue); in buildSchedGraph()
996 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V); in buildSchedGraph()
1004 if (Stores.size() + Loads.size() >= HugeRegion) { in buildSchedGraph()
1006 reduceHugeMemNodeMaps(Stores, Loads, getReductionSize()); in buildSchedGraph()
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| D | WinEHPrepare.cpp | 83 DenseMap<BasicBlock *, Value *> &Loads, Function &F);
1108 DenseMap<BasicBlock *, Value *> Loads; in insertPHILoads() local
1116 replaceUseWithLoad(PN, U, SpillSlot, Loads, F); in insertPHILoads()
1177 DenseMap<BasicBlock *, Value *> &Loads, in replaceUseWithLoad() argument
1237 Value *&Load = Loads[IncomingBlock]; in replaceUseWithLoad()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86PreAMXConfig.cpp | 108 bool checkVolatileModel(SmallSet<Value *, 4> &Loads, IntrinsicInst *Store,
215 bool X86PreAMXConfig::checkVolatileModel(SmallSet<Value *, 4> &Loads, in checkVolatileModel() argument
222 return (Loads.size() == 1) && Loads.contains(ST); in checkVolatileModel()
228 if (!Loads.erase(Op)) in checkVolatileModel()
234 return Loads.empty() && (ST == cast<Value>(KeyAMX)); in checkVolatileModel()
273 SmallSet<Value *, 4> Loads; in getShapesAndConfigPosEnd() local
283 Loads.insert(II); in getShapesAndConfigPosEnd()
285 if (!checkVolatileModel(Loads, II, KeyAMX)) in getShapesAndConfigPosEnd()
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| D | X86ScheduleAtom.td | 43 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
161 // Loads, stores, and moves, not folded with other operations.
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| D | X86Schedule.td | 123 // Loads, stores, and moves, not folded with other operations.
548 // Conditional SIMD Packed Loads and Stores wrappers.
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMParallelDSP.cpp | 200 SmallVector<LoadInst*, 4> Loads; member in __anon227087a10111::WidenedLoad
205 append_range(Loads, Lds); in WidenedLoad()
229 LoadInst* CreateWideLoad(MemInstList &Loads, IntegerType *LoadTy);
343 SmallVector<LoadInst*, 8> Loads; in RecordMemoryOps() local
358 Loads.push_back(Ld); in RecordMemoryOps()
361 if (Loads.empty() || Loads.size() > NumLoadLimit) in RecordMemoryOps()
371 for (auto Read : Loads) { in RecordMemoryOps()
404 for (auto *Base : Loads) { in RecordMemoryOps()
405 for (auto *Offset : Loads) { in RecordMemoryOps()
728 LoadInst* ARMParallelDSP::CreateWideLoad(MemInstList &Loads, in CreateWideLoad() argument
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| D | ARMSelectionDAGInfo.cpp | 205 SDValue Loads[6]; in EmitTargetCodeForMemcpy() local
260 Loads[i] = DAG.getLoad(VT, dl, Chain, in EmitTargetCodeForMemcpy()
264 TFOps[i] = Loads[i].getValue(1); in EmitTargetCodeForMemcpy()
277 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], in EmitTargetCodeForMemcpy()
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| D | ARMScheduleM4.td | 47 // Loads, MAC's and DIV all get a higher latency of 2
106 // Loads still take 2 cycles.
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| D | DemoteRegToStack.cpp | 69 DenseMap<BasicBlock*, Value*> Loads; in DemoteRegToStack() local
72 Value *&V = Loads[PN->getIncomingBlock(i)]; in DemoteRegToStack()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 269 SmallVector<SDNode*, 4> Loads; in ClusterNeighboringLoads() local
273 Loads.push_back(BaseLoad); in ClusterNeighboringLoads()
279 Loads.push_back(Load); in ClusterNeighboringLoads()
288 SDNode *Lead = Loads[0]; in ClusterNeighboringLoads()
292 for (unsigned I = 1, E = Loads.size(); I != E; ++I) { in ClusterNeighboringLoads()
294 SDNode *Load = Loads[I]; in ClusterNeighboringLoads()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| D | AliasAnalysisEvaluator.cpp | 104 SetVector<Value *> Loads; in runInternal() local
115 Loads.insert(&Inst); in runInternal()
179 for (Value *Load : Loads) { in runInternal()
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| D | LoopAccessAnalysis.cpp | 1806 SmallVector<LoadInst *, 16> Loads; in analyzeLoop() local
1880 Loads.push_back(Ld); in analyzeLoop()
1973 for (LoadInst *LD : Loads) { in analyzeLoop()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
| D | ArgumentPromotion.cpp | 658 SmallVector<LoadInst *, 16> Loads; in isSafeToPromoteArgument() local
667 Loads.push_back(LI); in isSafeToPromoteArgument()
696 Loads.push_back(LI); in isSafeToPromoteArgument()
728 if (Loads.empty()) in isSafeToPromoteArgument()
740 for (LoadInst *Load : Loads) { in isSafeToPromoteArgument()
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| D | GlobalOpt.cpp | 1334 SmallVector<LoadInst *, 4> Loads; in isPointerValueDeadOnEntryToFunction() local
1340 Loads.push_back(LI); in isPointerValueDeadOnEntryToFunction()
1355 Loads.push_back(LI); in isPointerValueDeadOnEntryToFunction()
1378 if (Loads.size() * Stores.size() > Threshold) in isPointerValueDeadOnEntryToFunction()
1381 for (auto *L : Loads) { in isPointerValueDeadOnEntryToFunction()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVScheduleV.td | 12 // 7. Vector Loads and Stores
51 // 7.7. Vector Unit-stride Fault-Only-First Loads
258 // 7. Vector Loads and Stores
482 // 7. Vector Loads and Stores
662 // 7. Vector Loads and Stores
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SMEInstrInfo.td | 71 // Loads and stores
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 29 def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
30 def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
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| D | PPCScheduleP9.td | 331 // Loads can have 4, 5 or 6 cycles of latency.
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| /freebsd-12-stable/contrib/gcc/config/arm/ |
| D | arm926ejs.md | 122 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
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| D | arm1026ejs.md | 162 ;; Loads and stores which use a scaled register offset or scaled
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| /freebsd-12-stable/contrib/gcc/config/rs6000/ |
| D | 8540.md | 152 ;; Loads
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| /freebsd-12-stable/crypto/heimdal/kadmin/ |
| D | kadmin-commands.in | 111 help = "Loads a previously dumped file. Local (-l) mode only."
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCInstrFormats.td | 427 // aa - Incrementing mode. Loads and stores can write-back address pre- or
431 // Loads and Stores support different memory addressing modes:
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | SROA.cpp | 3812 SmallVector<LoadInst *, 4> Loads; in presplitLoadsAndStores() local
3876 Loads.push_back(LI); in presplitLoadsAndStores()
3972 llvm::erase_if(Loads, [&UnsplittableLoads](LoadInst *LI) { in presplitLoadsAndStores()
3978 if (Loads.empty() && Stores.empty()) in presplitLoadsAndStores()
4003 for (LoadInst *LI : Loads) { in presplitLoadsAndStores()
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