| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCTargetDesc.cpp | 150 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) { in HexagonConvertUnits() argument
162 return (*Lanes = 4, CVI_XLANE); in HexagonConvertUnits()
165 return (*Lanes = 2, CVI_XLANE | CVI_MPY0); in HexagonConvertUnits()
167 return (*Lanes = 2, CVI_MPY0); in HexagonConvertUnits()
169 return (*Lanes = 2, CVI_XLANE); in HexagonConvertUnits()
174 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
177 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT); in HexagonConvertUnits()
180 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
182 return (*Lanes = 1, CVI_ZW); in HexagonConvertUnits()
184 return (*Lanes = 1, CVI_XLANE); in HexagonConvertUnits()
[all …]
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| D | HexagonShuffler.cpp | 115 unsigned Lanes; in HexagonCVIResource() local
116 const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes); in HexagonCVIResource()
118 if (Units == 0 && Lanes == 0) { in HexagonCVIResource()
129 setLanes(Lanes); in HexagonCVIResource()
137 unsigned Lanes; member
141 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
143 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
156 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
336 inst.Lanes = I->CVI.getLanes(); in ValidResourceUsage()
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| D | HexagonShuffler.h | 86 unsigned Lanes; variable
92 void setLanes(unsigned l) { Lanes = l; } in setLanes()
102 unsigned getLanes() const { return Lanes; } in getLanes()
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| D | HexagonMCTargetDesc.h | 100 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
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| /freebsd-12-stable/contrib/llvm-project/clang/utils/TableGen/ |
| D | MveEmitter.cpp | 290 unsigned Lanes; member in __anon7f5bce5f0111::VectorType
293 VectorType(const ScalarType *Element, unsigned Lanes) in VectorType() argument
294 : CRegularNamedType(TypeKind::Vector), Element(Element), Lanes(Lanes) {} in VectorType()
295 unsigned sizeInBits() const override { return Lanes * Element->sizeInBits(); } in sizeInBits()
296 unsigned lanes() const { return Lanes; } in lanes()
300 return Element->cNameBase() + "x" + utostr(Lanes); in cNameBase()
304 utostr(Lanes) + ")"; in llvmName()
342 unsigned Lanes; member in __anon7f5bce5f0111::PredicateType
345 PredicateType(unsigned Lanes) in PredicateType() argument
346 : CRegularNamedType(TypeKind::Predicate), Lanes(Lanes) {} in PredicateType()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 396 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
401 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
443 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
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| D | SIMachineFunctionInfo.h | 464 SmallVector<MCPhysReg, 32> Lanes;
544 : I->second.Lanes[Lane];
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| D | SIISelLowering.cpp | 7373 SmallVector<SDValue, 3> Lanes; in LowerINTRINSIC_W_CHAIN() local
7374 DAG.ExtractVectorElements(Op, Lanes, 0, 3); in LowerINTRINSIC_W_CHAIN()
7375 if (Lanes[0].getValueSizeInBits() == 32) { in LowerINTRINSIC_W_CHAIN()
7377 Ops.push_back(DAG.getBitcast(MVT::i32, Lanes[I])); in LowerINTRINSIC_W_CHAIN()
7383 { Lanes[0], Lanes[1] }))); in LowerINTRINSIC_W_CHAIN()
7384 Ops.push_back(Lanes[2]); in LowerINTRINSIC_W_CHAIN()
7390 { Elt0, Lanes[0] }))); in LowerINTRINSIC_W_CHAIN()
7394 { Lanes[1], Lanes[2] }))); in LowerINTRINSIC_W_CHAIN()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 757 int Lanes = 1; in getCastInstrCost() local
759 Lanes = SrcTy.getVectorNumElements(); in getCastInstrCost()
762 return Lanes; in getCastInstrCost()
764 return Lanes * CallCost; in getCastInstrCost()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 220 // Vector Add Across Lanes
225 // Vector Long Add Across Lanes
320 // Vector Max Across Lanes
336 // Vector Min Across Lanes
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 3056 unsigned Lanes = FVTy->getNumElements(); in ConstantFoldFixedVectorCall() local
3064 for (unsigned i = 0; i < Lanes; i++) { in ConstantFoldFixedVectorCall()
3078 unsigned Lanes = FVTy->getNumElements(); in ConstantFoldFixedVectorCall() local
3083 for (unsigned i = 0; i < Lanes; i++) { in ConstantFoldFixedVectorCall()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 2673 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0) in analyzeValue() local
2675 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
3026 LaneBitmask Lanes) const { in usesLanes()
3035 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any()) in usesLanes()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 1782 const size_t Lanes = Op.getNumOperands(); in LowerBUILD_VECTOR() local
1869 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
2010 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 2598 unsigned Lanes = IsUniform ? 1 : VF.getKnownMinValue(); in buildScalarSteps() local
2633 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in buildScalarSteps()
4755 unsigned Lanes = IsUniform ? 1 : State.VF.getKnownMinValue(); in widenPHIInstruction() local
4782 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in widenPHIInstruction()
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| D | SLPVectorizer.cpp | 1386 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) in getVL() local
|