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Searched refs:LSL (Results 1 – 25 of 39) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ExpandImm.cpp82 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
97 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
228 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
237 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
280 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
298 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
371 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImm()
DAArch64SchedPredicates.td48 def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
362 // ORR Rd, ZR, Rm, LSL #0
416 // MOVI Vd, #0, LSL #0
DAArch64RegisterInfo.td1140 // LSL(8|16|32|64)
1141 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1142 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1143 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1144 def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1145 def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1146 def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1147 def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1148 def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
DAArch64ExpandPseudoInsts.cpp945 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in expandMI()
1140 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
1145 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
DAArch64FastISel.cpp720 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
802 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
847 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
1057 Addr.getOffsetReg(), AArch64_AM::LSL, in simplifyAddress()
1238 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL, in emitAddSub()
1252 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1720 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()
DAArch64RegisterInfo.cpp560 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); in materializeFrameBaseRegister()
DAArch64InstrInfo.cpp898 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
3305 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in copyPhysReg()
3311 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
3316 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
3399 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
3403 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
4062 AArch64_AM::getShifterImm(AArch64_AM::LSL, LocalShiftSize)); in emitFrameOffsetAdj()
DAArch64ISelDAGToDAG.cpp450 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed()
497 return AArch64_AM::LSL; in getShiftTypeForNode()
2244 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) { in getUsefulBitsFromOrWithShiftedReg()
3543 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); in Select()
DAArch64FrameLowering.cpp1321 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in emitPrologue()
1329 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 16)) in emitPrologue()
DAArch64SchedCyclone.td157 // EXAMPLE: ADDrs Xn, Xm LSL #imm
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h34 LSL = 0, enumerator
55 case AArch64_AM::LSL: return "lsl"; in getShiftExtendName()
76 case 0: return AArch64_AM::LSL; in getShiftType()
104 case AArch64_AM::LSL: STEnc = 0; break; in getShifterImm()
DAArch64MCCodeEmitter.cpp272 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
550 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL && in getImm8OptLsl()
DAArch64InstPrinter.cpp1055 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && in printShifter()
1677 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && in printImm8OptLsl()
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
DEmulateInstructionARM64.cpp84 static inline uint64_t LSL(uint64_t x, integer shift) { in LSL() function
775 idx = LSL(llvm::SignExtend64<7>(imm7), scale); in EmulateLDPSTP()
950 offset = LSL(Bits32(opcode, 21, 10), size); in EmulateLDRSTRImm()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.h38 LSL, ///< Logical shift left. enumerator
DAVRInstrInfo.td57 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
1671 // 8-bit LSL is an alias of ADD Rd, Rd
1822 // LSL Rd
1826 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
2166 // Lowering of 'lsl' node to 'LSL' instruction.
2167 // LSL is an alias of 'ADD Rd, Rd'
DAVRISelLowering.cpp246 NODE(LSL); in getTargetNodeName()
331 Opc8 = AVRISD::LSL; in LowerShifts()
/freebsd-12-stable/contrib/gcc/config/arm/
Darm1026ejs.md164 ;; those that are base + offset with LSL of 0 or 2, or base - offset
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
Darm1020e.md164 ;; those that are base + offset with LSL of 0 or 2, or base - offset
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1285 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
1338 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1385 ET == AArch64_AM::LSL) && in isExtend()
1404 ET == AArch64_AM::LSL) && in isExtendLSL64()
1412 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1433 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1444 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
1455 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1467 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1479 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
[all …]
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
DARMUtils.h100 static inline uint32_t LSL(const uint32_t value, const uint32_t amount, in LSL() function
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonConstPropagation.cpp2525 LatticeCell LSL, LSH; in evaluateHexRSEQ32() local
2526 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
2528 if (LSL.isProperty() || LSH.isProperty()) in evaluateHexRSEQ32()
2531 unsigned LN = LSL.size(), HN = LSH.size(); in evaluateHexRSEQ32()
2534 bool Eval = constToInt(LSL.Values[i], LoVs[i]); in evaluateHexRSEQ32()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h494 LSL, enumerator
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMScheduleM7.td338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
DARMInstrThumb.td1161 // LSL immediate
1172 // LSL register

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