Searched refs:LHS1 (Results 1 – 5 of 5) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 1433 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in foldLogicOfFCmps() local
1437 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1457 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1461 return getFCmpValue(NewPred, LHS0, LHS1, Builder); in foldLogicOfFCmps()
1471 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP())) in foldLogicOfFCmps()
2376 Value *LHS1 = LHS->getOperand(1), *RHS1 = RHS->getOperand(1); in foldOrOfICmps() local
2377 auto *LHSC = dyn_cast<ConstantInt>(LHS1); in foldOrOfICmps()
2433 if (LHS0 == RHS1 && LHS1 == RHS0) in foldOrOfICmps()
2435 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldOrOfICmps()
2438 return getNewICmpValue(Code, IsSigned, LHS0, LHS1, Builder); in foldOrOfICmps()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1907 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1923 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) || in simplifyAndOrOfFCmps()
1924 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1))) in simplifyAndOrOfFCmps()
1935 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) || in simplifyAndOrOfFCmps()
1936 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1))) in simplifyAndOrOfFCmps()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 677 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
705 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5572 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5574 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5581 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
11779 Register LHS1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
11783 .addReg(LHS1) in EmitInstrWithCustomInserter()
11793 .addReg(LHS1) in EmitInstrWithCustomInserter()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 6084 SDValue LHS1, LHS2; in splitVectorIntBinary() local
6085 std::tie(LHS1, LHS2) = splitVector(Op.getOperand(0), DAG, dl); in splitVectorIntBinary()
6094 DAG.getNode(Op.getOpcode(), dl, LoVT, LHS1, RHS1), in splitVectorIntBinary()
22905 SDValue LHS1, LHS2; in splitIntVSETCC() local
22906 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitIntVSETCC()
22916 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
44110 SDValue LHS1 = RHS.getOperand(0); in combineVectorHADDSUB() local
44113 (LHS1 == RHS1 || LHS1.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
44117 LHS1.isUndef() ? RHS1 : LHS1); in combineVectorHADDSUB()
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