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Searched refs:LC1 (Results 1 – 14 of 14) sorted by relevance

/freebsd-12-stable/sys/dev/xdma/controller/
Dpl330.h65 #define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */ macro
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
DHexagonRegisterInfo.td151 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
182 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
399 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
DHexagonRegisterInfo.cpp165 Reserved.set(Hexagon::LC1); // C3 in getReservedRegs()
DHexagonHardwareLoops.cpp999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
1000 static const unsigned Regs1[] = { LC1, SA1 }; in isInvalidLoopOperation()
DHexagonISelLowering.cpp330 .Case("lc1", Hexagon::LC1) in getRegisterByName()
DHexagonDepInstrInfo.td5021 let Uses = [LC0, LC1, SA0, SA1];
5022 let Defs = [LC0, LC1, P3, PC, USR];
5030 let Uses = [LC1, SA1];
5031 let Defs = [LC1, PC];
5656 let Defs = [LC1, SA1];
5674 let Defs = [LC1, SA1];
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.h112 Hexagon::LC1 == R); in isLoopRegister()
DHexagonMCChecker.cpp49 Defs[Hexagon::LC1].insert(Unconditional); in init()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp308 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; in softenSetCCOperands() local
313 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
319 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
325 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
331 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
337 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
343 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
351 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
360 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
372 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp661 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()
/freebsd-12-stable/sys/dev/usb/
Dusbdevs3544 product ONSPEC CFSM_COMBO 0xa109 USB to CF + SM Combo (LC1)
/freebsd-12-stable/contrib/gcc/
DChangeLog-20064862 REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
4881 (rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
/freebsd-12-stable/contrib/gcc/doc/
Dmd.texi2191 LC0 or LC1.