Searched refs:LC0 (Results 1 – 14 of 14) sorted by relevance
| /freebsd-12-stable/sys/dev/xdma/controller/ |
| D | pl330.h | 64 #define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */ macro
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| D | pl330.c | 169 __func__, pending, READ4(sc, LC0(0)), in pl330_intr()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
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| D | HexagonRegisterInfo.td | 149 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>;
181 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
399 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
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| D | HexagonRegisterInfo.cpp | 163 Reserved.set(Hexagon::LC0); // C1 in getReservedRegs()
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| D | HexagonHardwareLoops.cpp | 999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
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| D | HexagonISelLowering.cpp | 328 .Case("lc0", Hexagon::LC0) in getRegisterByName()
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| D | HexagonDepInstrInfo.td | 5010 let Uses = [LC0, SA0];
5011 let Defs = [LC0, P3, PC, USR];
5021 let Uses = [LC0, LC1, SA0, SA1];
5022 let Defs = [LC0, LC1, P3, PC, USR];
5621 let Defs = [LC0, SA0, USR];
5639 let Defs = [LC0, SA0, USR];
5703 let Defs = [LC0, P3, SA0, USR];
5722 let Defs = [LC0, P3, SA0, USR];
5740 let Defs = [LC0, P3, SA0, USR];
5759 let Defs = [LC0, P3, SA0, USR];
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 111 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
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| D | HexagonMCChecker.cpp | 45 Defs[Hexagon::LC0].insert(Unconditional); in init()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 661 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()
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| /freebsd-12-stable/contrib/gdb/gdb/doc/ |
| D | stabs.texinfo | 351 22 LC0:
367 38 sethi %hi(LC0),%o1
368 39 or %o1,%lo(LC0),%o0
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| /freebsd-12-stable/contrib/gcc/doc/ |
| D | md.texi | 2191 LC0 or LC1.
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| /freebsd-12-stable/contrib/gcc/ |
| D | ChangeLog-2006 | 4862 REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
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