Searched refs:IsRet (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.h | 510 bool IsFixed, bool IsRet, Type *OrigTy,
515 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
519 bool IsRet, CallLoweringInfo *CLI,
|
| D | RISCVISelLowering.cpp | 7074 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, in CC_RISCV() argument
7082 if (!LocVT.isVector() && IsRet && ValNo > 1) in CC_RISCV()
7225 if (IsRet) in CC_RISCV()
7298 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
7312 if (IsRet) in analyzeInputArgs()
7319 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this, in analyzeInputArgs()
7330 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
7345 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, in analyzeOutputArgs()
7495 bool IsFixed, bool IsRet, Type *OrigTy, in CC_RISCV_FastCC() argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 2330 bit IsRet = isRet;
2502 let ColFields = ["IsRet"];
|