Searched refs:InputVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 3847 EVT InputVT = LHS.getValueType(); in getSETCCInGPR() local
3848 if (InputVT != MVT::i32 && InputVT != MVT::i64) in getSETCCInGPR()
3853 CC = ISD::getSetCCInverse(CC, InputVT); in getSETCCInGPR()
3855 bool Inputs32Bit = InputVT == MVT::i32; in getSETCCInGPR()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 4348 SDValue InputVT = DAG.getValueType(MemVT); in LowerMGATHER() local
4364 InputVT = DAG.getValueType(MemVT.changeTypeToInteger()); in LowerMGATHER()
4379 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger()); in LowerMGATHER()
4402 SDValue Ops[] = {Chain, Mask, BasePtr, Index, InputVT}; in LowerMGATHER()
4453 SDValue InputVT = DAG.getValueType(MemVT); in LowerMSCATTER() local
4469 InputVT = DAG.getValueType(MemVT.changeTypeToInteger()); in LowerMSCATTER()
4484 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger()); in LowerMSCATTER()
4502 SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, InputVT}; in LowerMSCATTER()
14740 SDValue InputVT = DAG.getValueType(DataVT); in performST1Combine() local
14747 InputVT = DAG.getValueType(HwSrcVt); in performST1Combine()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 13262 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements); in lowerShuffleAsSpecificZeroOrAnyExtend() local
13263 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT) in lowerShuffleAsSpecificZeroOrAnyExtend()
13264 : getZeroVector(InputVT, Subtarget, DAG, DL); in lowerShuffleAsSpecificZeroOrAnyExtend()
13265 InputV = DAG.getBitcast(InputVT, InputV); in lowerShuffleAsSpecificZeroOrAnyExtend()
13266 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext); in lowerShuffleAsSpecificZeroOrAnyExtend()
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