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Searched refs:Imm (Results 1 – 25 of 319) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
123 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
129 inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
132 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
135 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
142 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
147 if (Imm & 63U) { in getSOImmValRotate()
148 unsigned TZ2 = countTrailingZeros(Imm & ~63U); in getSOImmValRotate()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
46 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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DMipsISelDAGToDAG.h98 virtual bool selectVSplat(SDNode *N, APInt &Imm,
101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
117 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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DMipsSEISelDAGToDAG.h96 bool selectVSplat(SDNode *N, APInt &Imm,
99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
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DMipsISelDAGToDAG.cpp154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument
160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp73 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand() local
74 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
75 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
134 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
135 if (Imm != 0) { in printOffset()
144 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset() local
145 if (Imm != 0) { in printFlatOffset()
207 auto Imm = MI->getOperand(OpNo).getImm(); in printCPol() local
208 if (Imm & CPol::GLC) in printCPol()
210 if (Imm & CPol::SLC) in printCPol()
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DSIMCCodeEmitter.cpp90 static uint32_t getIntInlineImmEncoding(IntTy Imm) { in getIntInlineImmEncoding() argument
91 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
92 return 128 + Imm; in getIntInlineImmEncoding()
94 if (Imm >= -16 && Imm <= -1) in getIntInlineImmEncoding()
95 return 192 + std::abs(Imm); in getIntInlineImmEncoding()
216 int64_t Imm; in getLitEncoding() local
222 Imm = C->getValue(); in getLitEncoding()
230 Imm = MO.getImm(); in getLitEncoding()
244 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); in getLitEncoding()
251 return getLit64Encoding(static_cast<uint64_t>(Imm), STI); in getLitEncoding()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, in decodeCondBrTarget() argument
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, in decodeDirectBrTarget() argument
75 int32_t Offset = SignExtend32<24>(Imm); in decodeDirectBrTarget()
200 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
202 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
203 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
208 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
210 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()
211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
172 if (!isUInt<N>(Imm)) in decodeUImmOperand()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
180 if (!isUInt<N>(Imm)) in decodeSImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
188 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU2ImmOperand() argument
193 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ExpandImm.cpp22 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { in getChunk() argument
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk()
125 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { in updateImm() argument
130 Imm &= ~(Mask << (Idx * 16)); in updateImm()
133 Imm |= Mask << (Idx * 16); in updateImm()
135 return Imm; in updateImm()
245 static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize, in expandMOVImmSimple() argument
259 Imm = ~Imm; in expandMOVImmSimple()
264 Imm &= (1LL << 32) - 1; in expandMOVImmSimple()
271 if (Imm != 0) { in expandMOVImmSimple()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
DNVPTXInstPrinter.cpp101 int64_t Imm = MO.getImm(); in printCvtMode() local
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
151 int64_t Imm = MO.getImm(); in printCmpMode() local
155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode()
225 int Imm = (int) MO.getImm(); in printLdStCode() local
227 if (Imm) in printLdStCode()
230 switch (Imm) { in printLdStCode()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
80 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
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DX86ShuffleDecode.cpp25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument
33 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
34 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
35 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
98 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, in DecodePSLLDQMask() argument
105 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
110 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, in DecodePSRLDQMask() argument
116 unsigned Base = i + Imm; in DecodePSRLDQMask()
123 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, in DecodePALIGNRMask() argument
129 unsigned Base = i + Imm; in DecodePALIGNRMask()
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DX86ATTInstPrinter.cpp85 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); in printVecCompareInstr() local
98 if (Imm >= 0 && Imm <= 7) { in printVecCompareInstr()
156 if (Imm >= 0 && Imm <= 31) { in printVecCompareInstr()
221 if (Imm >= 0 && Imm <= 7) { in printVecCompareInstr()
298 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) { in printVecCompareInstr()
360 int64_t Imm = Op.getImm(); in printOperand() local
361 O << markup("<imm:") << '$' << formatImm(Imm) << markup(">"); in printOperand()
369 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) { in printOperand()
371 if (Imm == (int16_t)(Imm)) in printOperand()
372 *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm); in printOperand()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp293 ImmOp Imm; member
311 Imm = o.Imm; in RISCVOperand()
340 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, in evaluateConstantImm()
344 return RE->evaluateAsConstant(Imm); in evaluateConstantImm()
349 Imm = CE->getValue(); in evaluateConstantImm()
359 int64_t Imm; in isBareSimmNLsb0() local
363 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); in isBareSimmNLsb0()
368 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
375 int64_t Imm; in isBareSymbol() local
378 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isBareSymbol()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, in decodeSoppBrTarget() argument
77 APInt SignedOffset(18, Imm * 4, true); in decodeSoppBrTarget()
82 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSoppBrTarget()
85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, in decodeSMEMOffset() argument
90 Offset = Imm & 0xFFFFF; in decodeSMEMOffset()
92 Offset = SignExtend64<21>(Imm); in decodeSMEMOffset()
105 unsigned Imm, \
109 return addOperand(Inst, DAsm->DecoderName(Imm)); \
148 unsigned Imm, in DECODE_OPERAND_REG()
152 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); in DECODE_OPERAND_REG()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h52 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, in getIntImmCost() argument
55 if (Imm == 0) in getIntImmCost()
57 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
59 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
61 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
62 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
71 const APInt &Imm, Type *Ty,
74 return getIntImmCost(Imm, Ty, CostKind);
78 const APInt &Imm, Type *Ty, in getIntImmCostIntrin() argument
80 return getIntImmCost(Imm, Ty, CostKind); in getIntImmCostIntrin()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp270 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
272 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
274 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
279 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, in decodeUImmNonZeroOperand() argument
282 if (Imm == 0) in decodeUImmNonZeroOperand()
284 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); in decodeUImmNonZeroOperand()
288 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
290 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()
293 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
298 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, in decodeSImmNonZeroOperand() argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
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DRISCVTargetTransformInfo.cpp18 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, in getIntImmCost() argument
24 if (Imm == 0) in getIntImmCost()
29 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), in getIntImmCost()
34 const APInt &Imm, Type *Ty, in getIntImmCostInst() argument
41 if (Imm == 0) in getIntImmCostInst()
77 if (Imm.getMinSignedBits() <= 64 && in getIntImmCostInst()
78 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { in getIntImmCostInst()
84 return getIntImmCost(Imm, Ty, CostKind); in getIntImmCostInst()
93 const APInt &Imm, Type *Ty, in getIntImmCostIntrin() argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp33 InstructionCost SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, in getIntImmCost() argument
46 if (Imm == 0) in getIntImmCost()
49 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
51 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
57 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost()
67 const APInt &Imm, Type *Ty, in getIntImmCostInst() argument
92 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCostInst()
97 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()
102 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCostInst()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
DBPFInstPrinter.cpp76 auto Imm = OffsetOp.getImm(); in printMemOperand() local
77 if (Imm >= 0) in printMemOperand()
78 O << " + " << formatImm(Imm); in printMemOperand()
80 O << " - " << formatImm(-Imm); in printMemOperand()
101 int16_t Imm = Op.getImm(); in printBrTargetOperand() local
102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
DCSKYAsmParser.cpp102 ImmOp Imm; member
117 Imm = o.Imm; in CSKYOperand()
130 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) { in evaluateConstantImm()
132 Imm = CE->getValue(); in evaluateConstantImm()
143 int64_t Imm; in isUImm() local
144 bool IsConstantImm = evaluateConstantImm(getImm(), Imm); in isUImm()
145 return IsConstantImm && isShiftedUInt<num, shift>(Imm); in isUImm()
152 int64_t Imm; in isOImm() local
153 bool IsConstantImm = evaluateConstantImm(getImm(), Imm); in isOImm()
154 return IsConstantImm && isUInt<num>(Imm - 1); in isOImm()
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12345678910>>...13