1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: stable/12/sys/arm64/include/armreg.h 372168 2022-06-22 15:58:54Z jhibbits $ 31 */ 32 33 #ifndef _MACHINE_ARMREG_H_ 34 #define _MACHINE_ARMREG_H_ 35 36 #define INSN_SIZE 4 37 38 #define READ_SPECIALREG(reg) \ 39 ({ uint64_t val; \ 40 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 41 val; \ 42 }) 43 #define WRITE_SPECIALREG(reg, val) \ 44 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 45 46 #define UL(x) UINT64_C(x) 47 48 /* CCSIDR_EL1 - Cache Size ID Register */ 49 #define CCSIDR_NumSets_MASK 0x0FFFE000 50 #define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 51 #define CCSIDR_NumSets_SHIFT 13 52 #define CCSIDR_NumSets64_SHIFT 32 53 #define CCSIDR_Assoc_MASK 0x00001FF8 54 #define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 55 #define CCSIDR_Assoc_SHIFT 3 56 #define CCSIDR_Assoc64_SHIFT 3 57 #define CCSIDR_LineSize_MASK 0x7 58 #define CCSIDR_NSETS(idr) \ 59 (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) 60 #define CCSIDR_ASSOC(idr) \ 61 (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) 62 #define CCSIDR_NSETS_64(idr) \ 63 (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) 64 #define CCSIDR_ASSOC_64(idr) \ 65 (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) 66 67 /* CLIDR_EL1 - Cache level ID register */ 68 #define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ 69 #define CLIDR_CTYPE_IO 0x1 /* Instruction only */ 70 #define CLIDR_CTYPE_DO 0x2 /* Data only */ 71 #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ 72 #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ 73 74 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 75 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 76 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 77 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 78 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 79 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 80 81 /* CPACR_EL1 */ 82 #define CPACR_FPEN_MASK (0x3 << 20) 83 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 84 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 85 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 86 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 87 #define CPACR_TTA (0x1 << 28) 88 89 /* CSSELR_EL1 - Cache size selection register */ 90 #define CSSELR_Level(i) (i << 1) 91 #define CSSELR_InD 0x00000001 92 93 /* CTR_EL0 - Cache Type Register */ 94 #define CTR_DLINE_SHIFT 16 95 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 96 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 97 #define CTR_ILINE_SHIFT 0 98 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 99 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 100 101 /* DAIF - Interrupt Mask Bits */ 102 #define DAIF_D_MASKED (1 << 9) 103 #define DAIF_A_MASKED (1 << 8) 104 #define DAIF_I_MASKED (1 << 7) 105 #define DAIF_F_MASKED (1 << 6) 106 107 /* DCZID_EL0 - Data Cache Zero ID register */ 108 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 109 #define DCZID_BS_SHIFT 0 110 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 111 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 112 113 /* ESR_ELx */ 114 #define ESR_ELx_ISS_MASK 0x00ffffff 115 #define ISS_INSN_FnV (0x01 << 10) 116 #define ISS_INSN_EA (0x01 << 9) 117 #define ISS_INSN_S1PTW (0x01 << 7) 118 #define ISS_INSN_IFSC_MASK (0x1f << 0) 119 #define ISS_DATA_ISV (0x01 << 24) 120 #define ISS_DATA_SAS_MASK (0x03 << 22) 121 #define ISS_DATA_SSE (0x01 << 21) 122 #define ISS_DATA_SRT_MASK (0x1f << 16) 123 #define ISS_DATA_SF (0x01 << 15) 124 #define ISS_DATA_AR (0x01 << 14) 125 #define ISS_DATA_FnV (0x01 << 10) 126 #define ISS_DATA_EA (0x01 << 9) 127 #define ISS_DATA_CM (0x01 << 8) 128 #define ISS_DATA_S1PTW (0x01 << 7) 129 #define ISS_DATA_WnR (0x01 << 6) 130 #define ISS_DATA_DFSC_MASK (0x3f << 0) 131 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 132 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 133 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 134 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 135 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 136 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 137 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 138 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 139 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 140 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 141 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 142 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 143 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 144 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 145 #define ISS_DATA_DFSC_EXT (0x10 << 0) 146 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 147 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 148 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 149 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 150 #define ISS_DATA_DFSC_ECC (0x18 << 0) 151 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 152 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 153 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 154 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 155 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 156 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 157 #define ESR_ELx_IL (0x01 << 25) 158 #define ESR_ELx_EC_SHIFT 26 159 #define ESR_ELx_EC_MASK (0x3f << 26) 160 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 161 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 162 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 163 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 164 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 165 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 166 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 167 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 168 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 169 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 170 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 171 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 172 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 173 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 174 #define EXCP_SERROR 0x2f /* SError interrupt */ 175 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 176 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 177 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 178 #define EXCP_BRK 0x3c /* Breakpoint */ 179 180 /* ICC_CTLR_EL1 */ 181 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 182 183 /* ICC_IAR1_EL1 */ 184 #define ICC_IAR1_EL1_SPUR (0x03ff) 185 186 /* ICC_IGRPEN0_EL1 */ 187 #define ICC_IGRPEN0_EL1_EN (1U << 0) 188 189 /* ICC_PMR_EL1 */ 190 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 191 192 /* ICC_SGI1R_EL1 */ 193 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 194 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 195 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 196 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 197 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 198 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 199 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 200 201 /* ICC_SRE_EL1 */ 202 #define ICC_SRE_EL1_SRE (1U << 0) 203 204 /* ICC_SRE_EL2 */ 205 #define ICC_SRE_EL2_SRE (1U << 0) 206 #define ICC_SRE_EL2_EN (1U << 3) 207 208 /* ID_AA64DFR0_EL1 */ 209 #define ID_AA64DFR0_MASK UL(0x0000000ff0f0ffff) 210 #define ID_AA64DFR0_DebugVer_SHIFT 0 211 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 212 #define ID_AA64DFR0_DebugVer(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 213 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 214 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 215 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 216 #define ID_AA64DFR0_TraceVer_SHIFT 4 217 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 218 #define ID_AA64DFR0_TraceVer(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 219 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 220 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 221 #define ID_AA64DFR0_PMUVer_SHIFT 8 222 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 223 #define ID_AA64DFR0_PMUVer(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 224 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 225 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 226 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 227 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 228 #define ID_AA64DFR0_BRPs_SHIFT 12 229 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 230 #define ID_AA64DFR0_BRPs(x) \ 231 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 232 #define ID_AA64DFR0_WRPs_SHIFT 20 233 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 234 #define ID_AA64DFR0_WRPs(x) \ 235 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 236 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 237 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 238 #define ID_AA64DFR0_CTX_CMPs(x) \ 239 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 240 #define ID_AA64DFR0_PMSVer_SHIFT 32 241 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 242 #define ID_AA64DFR0_PMSVer(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 243 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 244 #define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 245 246 /* ID_AA64ISAR0_EL1 */ 247 #define ID_AA64ISAR0_MASK UL(0x0000fffff0fffff0) 248 #define ID_AA64ISAR0_AES_SHIFT 4 249 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 250 #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 251 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 252 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 253 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 254 #define ID_AA64ISAR0_SHA1_SHIFT 8 255 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 256 #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 257 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 258 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 259 #define ID_AA64ISAR0_SHA2_SHIFT 12 260 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 261 #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 262 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 263 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 264 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 265 #define ID_AA64ISAR0_CRC32_SHIFT 16 266 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 267 #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 268 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 269 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 270 #define ID_AA64ISAR0_Atomic_SHIFT 20 271 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 272 #define ID_AA64ISAR0_Atomic(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 273 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 274 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 275 #define ID_AA64ISAR0_RDM_SHIFT 28 276 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 277 #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 278 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 279 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 280 #define ID_AA64ISAR0_SHA3_SHIFT 32 281 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 282 #define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 283 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 284 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 285 #define ID_AA64ISAR0_SM3_SHIFT 36 286 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 287 #define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 288 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 289 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 290 #define ID_AA64ISAR0_SM4_SHIFT 40 291 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 292 #define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 293 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 294 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 295 #define ID_AA64ISAR0_DP_SHIFT 44 296 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 297 #define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 298 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 299 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 300 301 /* ID_AA64ISAR1_EL1 */ 302 #define ID_AA64ISAR1_MASK UL(0x00000000ffffffff) 303 #define ID_AA64ISAR1_DPB_SHIFT 0 304 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 305 #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 306 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 307 #define ID_AA64ISAR1_DPB_IMPL (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 308 #define ID_AA64ISAR1_APA_SHIFT 4 309 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 310 #define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 311 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 312 #define ID_AA64ISAR1_APA_IMPL (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 313 #define ID_AA64ISAR1_API_SHIFT 8 314 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 315 #define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 316 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 317 #define ID_AA64ISAR1_API_IMPL (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 318 #define ID_AA64ISAR1_JSCVT_SHIFT 12 319 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 320 #define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 321 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 322 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 323 #define ID_AA64ISAR1_FCMA_SHIFT 16 324 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 325 #define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 326 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 327 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 328 #define ID_AA64ISAR1_LRCPC_SHIFT 20 329 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 330 #define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 331 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 332 #define ID_AA64ISAR1_LRCPC_IMPL (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 333 #define ID_AA64ISAR1_GPA_SHIFT 24 334 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 335 #define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 336 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 337 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 338 #define ID_AA64ISAR1_GPI_SHIFT 28 339 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 340 #define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 341 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 342 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 343 344 /* ID_AA64MMFR0_EL1 */ 345 #define ID_AA64MMFR0_MASK UL(0x00000000ffffffff) 346 #define ID_AA64MMFR0_PARange_SHIFT 0 347 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 348 #define ID_AA64MMFR0_PARange(x) ((x) & ID_AA64MMFR0_PARange_MASK) 349 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 350 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 351 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 352 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 353 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 354 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 355 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 356 #define ID_AA64MMFR0_ASIDBits_SHIFT 4 357 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 358 #define ID_AA64MMFR0_ASIDBits(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 359 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 360 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 361 #define ID_AA64MMFR0_BigEnd_SHIFT 8 362 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 363 #define ID_AA64MMFR0_BigEnd(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 364 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 365 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 366 #define ID_AA64MMFR0_SNSMem_SHIFT 12 367 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 368 #define ID_AA64MMFR0_SNSMem(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 369 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 370 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 371 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 372 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 373 #define ID_AA64MMFR0_BigEndEL0(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 374 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 375 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 376 #define ID_AA64MMFR0_TGran16_SHIFT 20 377 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 378 #define ID_AA64MMFR0_TGran16(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 379 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 380 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 381 #define ID_AA64MMFR0_TGran64_SHIFT 24 382 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 383 #define ID_AA64MMFR0_TGran64(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 384 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 385 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 386 #define ID_AA64MMFR0_TGran4_SHIFT 28 387 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 388 #define ID_AA64MMFR0_TGran4(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 389 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 390 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 391 392 /* ID_AA64MMFR1_EL1 */ 393 #define ID_AA64MMFR1_MASK UL(0x00000000ffffffff) 394 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 395 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 396 #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 397 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 398 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 399 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 400 #define ID_AA64MMFR1_VMIDBits_SHIFT 4 401 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 402 #define ID_AA64MMFR1_VMIDBits(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 403 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 404 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 405 #define ID_AA64MMFR1_VH_SHIFT 8 406 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 407 #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 408 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 409 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 410 #define ID_AA64MMFR1_HPDS_SHIFT 12 411 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 412 #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 413 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 414 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 415 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 416 #define ID_AA64MMFR1_LO_SHIFT 16 417 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 418 #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 419 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 420 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 421 #define ID_AA64MMFR1_PAN_SHIFT 20 422 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 423 #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 424 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 425 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 426 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 427 #define ID_AA64MMFR1_SpecSEI_SHIFT 24 428 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 429 #define ID_AA64MMFR1_SpecSEI(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 430 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 431 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 432 #define ID_AA64MMFR1_XNX_SHIFT 28 433 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 434 #define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 435 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 436 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 437 438 /* ID_AA64MMFR2_EL1 */ 439 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 440 #define ID_AA64MMFR2_MASK UL(0x000000000fffffff) 441 #define ID_AA64MMFR2_CnP_SHIFT 0 442 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 443 #define ID_AA64MMFR2_CnP(x) ((x) & ID_AA64MMFR2_CnP_MASK) 444 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 445 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 446 #define ID_AA64MMFR2_UAO_SHIFT 4 447 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 448 #define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK) 449 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 450 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 451 #define ID_AA64MMFR2_LSM_SHIFT 8 452 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 453 #define ID_AA64MMFR2_LSM(x) ((x) & ID_AA64MMFR2_LSM_MASK) 454 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 455 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 456 #define ID_AA64MMFR2_IESB_SHIFT 12 457 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 458 #define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK) 459 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 460 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 461 #define ID_AA64MMFR2_VARange_SHIFT 16 462 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 463 #define ID_AA64MMFR2_VARange(x) ((x) & ID_AA64MMFR2_VARange_MASK) 464 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 465 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 466 #define ID_AA64MMFR2_CCIDX_SHIFT 20 467 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 468 #define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 469 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 470 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 471 #define ID_AA64MMFR2_NV_SHIFT 24 472 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 473 #define ID_AA64MMFR2_NV(x) ((x) & ID_AA64MMFR2_NV_MASK) 474 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 475 #define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 476 477 /* ID_AA64PFR0_EL1 */ 478 #define ID_AA64PFR0_MASK UL(0x0000000fffffffff) 479 #define ID_AA64PFR0_EL0_SHIFT 0 480 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 481 #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 482 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 483 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 484 #define ID_AA64PFR0_EL1_SHIFT 4 485 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 486 #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 487 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 488 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 489 #define ID_AA64PFR0_EL2_SHIFT 8 490 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 491 #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 492 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 493 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 494 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 495 #define ID_AA64PFR0_EL3_SHIFT 12 496 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 497 #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 498 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 499 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 500 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 501 #define ID_AA64PFR0_FP_SHIFT 16 502 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 503 #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 504 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 505 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 506 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 507 #define ID_AA64PFR0_AdvSIMD_SHIFT 20 508 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 509 #define ID_AA64PFR0_AdvSIMD(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 510 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 511 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 512 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 513 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 514 #define ID_AA64PFR0_GIC_SHIFT 24 515 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 516 #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 517 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 518 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 519 #define ID_AA64PFR0_RAS_SHIFT 28 520 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 521 #define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) 522 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 523 #define ID_AA64PFR0_RAS_V1 (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 524 #define ID_AA64PFR0_SVE_SHIFT 32 525 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 526 #define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) 527 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 528 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 529 530 /* MAIR_EL1 - Memory Attribute Indirection Register */ 531 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 532 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 533 #define MAIR_DEVICE_nGnRnE 0x00 534 #define MAIR_NORMAL_NC 0x44 535 #define MAIR_NORMAL_WT 0xbb 536 #define MAIR_NORMAL_WB 0xff 537 538 /* PAR_EL1 - Physical Address Register */ 539 #define PAR_F_SHIFT 0 540 #define PAR_F (0x1 << PAR_F_SHIFT) 541 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 542 /* When PAR_F == 0 (success) */ 543 #define PAR_SH_SHIFT 7 544 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 545 #define PAR_NS_SHIFT 9 546 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 547 #define PAR_PA_SHIFT 12 548 #define PAR_PA_MASK 0x0000fffffffff000 549 #define PAR_ATTR_SHIFT 56 550 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 551 /* When PAR_F == 1 (aborted) */ 552 #define PAR_FST_SHIFT 1 553 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 554 #define PAR_PTW_SHIFT 8 555 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 556 #define PAR_S_SHIFT 9 557 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 558 559 /* SCTLR_EL1 - System Control Register */ 560 #define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */ 561 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 562 563 #define SCTLR_M 0x00000001 564 #define SCTLR_A 0x00000002 565 #define SCTLR_C 0x00000004 566 #define SCTLR_SA 0x00000008 567 #define SCTLR_SA0 0x00000010 568 #define SCTLR_CP15BEN 0x00000020 569 /* Bit 6 is reserved */ 570 #define SCTLR_ITD 0x00000080 571 #define SCTLR_SED 0x00000100 572 #define SCTLR_UMA 0x00000200 573 /* Bit 10 is reserved */ 574 /* Bit 11 is reserved */ 575 #define SCTLR_I 0x00001000 576 #define SCTLR_EnDB 0x00002000 /* ARMv8.3 */ 577 #define SCTLR_DZE 0x00004000 578 #define SCTLR_UCT 0x00008000 579 #define SCTLR_nTWI 0x00010000 580 /* Bit 17 is reserved */ 581 #define SCTLR_nTWE 0x00040000 582 #define SCTLR_WXN 0x00080000 583 /* Bit 20 is reserved */ 584 #define SCTLR_IESB 0x00200000 /* ARMv8.2 */ 585 /* Bit 22 is reserved */ 586 #define SCTLR_SPAN 0x00800000 /* ARMv8.1 */ 587 #define SCTLR_EOE 0x01000000 588 #define SCTLR_EE 0x02000000 589 #define SCTLR_UCI 0x04000000 590 #define SCTLR_EnDA 0x08000000 /* ARMv8.3 */ 591 #define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */ 592 #define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */ 593 #define SCTLR_EnIB 0x40000000 /* ARMv8.3 */ 594 #define SCTLR_EnIA 0x80000000 /* ARMv8.3 */ 595 596 /* SPSR_EL1 */ 597 /* 598 * When the exception is taken in AArch64: 599 * M[3:2] is the exception level 600 * M[1] is unused 601 * M[0] is the SP select: 602 * 0: always SP0 603 * 1: current ELs SP 604 */ 605 #define PSR_M_EL0t 0x00000000 606 #define PSR_M_EL1t 0x00000004 607 #define PSR_M_EL1h 0x00000005 608 #define PSR_M_EL2t 0x00000008 609 #define PSR_M_EL2h 0x00000009 610 #define PSR_M_MASK 0x0000000f 611 612 #define PSR_AARCH32 0x00000010 613 #define PSR_F 0x00000040 614 #define PSR_I 0x00000080 615 #define PSR_A 0x00000100 616 #define PSR_D 0x00000200 617 #define PSR_IL 0x00100000 618 #define PSR_SS 0x00200000 619 #define PSR_V 0x10000000 620 #define PSR_C 0x20000000 621 #define PSR_Z 0x40000000 622 #define PSR_N 0x80000000 623 #define PSR_FLAGS 0xf0000000 624 625 /* TCR_EL1 - Translation Control Register */ 626 #define TCR_ASID_16 (1 << 36) 627 628 #define TCR_IPS_SHIFT 32 629 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 630 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 631 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 632 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 633 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 634 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 635 636 #define TCR_TG1_SHIFT 30 637 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 638 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 639 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 640 641 #define TCR_SH1_SHIFT 28 642 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 643 #define TCR_ORGN1_SHIFT 26 644 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 645 #define TCR_IRGN1_SHIFT 24 646 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 647 #define TCR_SH0_SHIFT 12 648 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 649 #define TCR_ORGN0_SHIFT 10 650 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 651 #define TCR_IRGN0_SHIFT 8 652 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 653 654 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 655 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 656 657 #ifdef SMP 658 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 659 #else 660 #define TCR_SMP_ATTRS 0 661 #endif 662 663 #define TCR_T1SZ_SHIFT 16 664 #define TCR_T0SZ_SHIFT 0 665 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 666 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 667 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 668 669 /* Saved Program Status Register */ 670 #define DBG_SPSR_SS (0x1 << 21) 671 672 /* Monitor Debug System Control Register */ 673 #define DBG_MDSCR_SS (0x1 << 0) 674 #define DBG_MDSCR_KDE (0x1 << 13) 675 #define DBG_MDSCR_MDE (0x1 << 15) 676 677 /* Perfomance Monitoring Counters */ 678 #define PMCR_E (1 << 0) /* Enable all counters */ 679 #define PMCR_P (1 << 1) /* Reset all counters */ 680 #define PMCR_C (1 << 2) /* Clock counter reset */ 681 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 682 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 683 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 684 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 685 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 686 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 687 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 688 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 689 #define PMCR_IDCODE_CORTEX_A57 0x01 690 #define PMCR_IDCODE_CORTEX_A72 0x02 691 #define PMCR_IDCODE_CORTEX_A53 0x03 692 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 693 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 694 695 #endif /* !_MACHINE_ARMREG_H_ */ 696