Searched refs:HiLHS (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 653 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
656 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
659 Regs.push_back(HiLHS); in split64BitValueForMapping()
663 .addDef(HiLHS) in split64BitValueForMapping()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1533 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp() local
1535 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1538 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1546 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
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| D | TargetLowering.cpp | 8493 SDValue HiLHS; in expandMULO() local
8499 HiLHS = in expandMULO()
8508 HiLHS = DAG.getConstant(0, dl, VT); in expandMULO()
8525 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; in expandMULO()
8528 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in expandMULO()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2960 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO() local
2962 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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