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Searched refs:HRI (Results 1 – 19 of 19) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp283 const HexagonRegisterInfo &HRI) { in needsStackFrame() argument
311 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) in needsStackFrame()
407 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in findShrunkPrologEpilog() local
439 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P) in findShrunkPrologEpilog()
440 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S) in findShrunkPrologEpilog()
444 if (needsStackFrame(I, CSR, HRI)) in findShrunkPrologEpilog()
508 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in emitPrologue() local
518 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs); in emitPrologue()
523 insertCSRRestoresInBlock(*EpilogB, CSI, HRI); in emitPrologue()
528 insertCSRRestoresInBlock(B, CSI, HRI); in emitPrologue()
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DHexagonInstrInfo.cpp132 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst() argument
133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
816 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg() local
877 LivePhysRegs LiveAtMI(HRI); in copyPhysReg()
879 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
908 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; in copyPhysReg()
1006 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo() local
1007 LivePhysRegs LiveIn(HRI), LiveOut(HRI); in expandPostRAPseudo()
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DHexagonVLIWPacketizer.cpp116 const HexagonRegisterInfo *HRI = nullptr; member in __anon71a2d5750111::HexagonPacketizer
139 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in INITIALIZE_PASS_DEPENDENCY()
208 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
307 if (DepReg == HRI->getRARegister()) in isCallDependent()
311 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister()) in isCallDependent()
492 if (HII->isValidOffset(Opc, NewOff, HRI)) { in useCallersSP()
543 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) in updateOffset()
666 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToNewValueStore()
716 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
728 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
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DHexagonBitSimplify.cpp440 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence() local
442 unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo); in parseRegSequence()
443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence()
904 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass() local
907 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
908 (void)HRI; in getFinalVRegClass()
909 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass()
910 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass()
1055 : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {} in RedundantInstrElimination()
1070 const HexagonRegisterInfo &HRI; member in __anon9730fdcd0511::RedundantInstrElimination
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DHexagonGenMux.cpp89 const HexagonRegisterInfo *HRI = nullptr; member in __anoneb7d58150111::HexagonGenMux
147 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I) in getSubRegs()
183 unsigned NR = HRI->getNumRegs(); in buildMaps()
355 LivePhysRegs LPR(*HRI); in genMuxInBlock()
358 for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S) in genMuxInBlock()
387 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction()
DHexagonVExtract.cpp104 const auto &HRI = *HST->getRegisterInfo(); in runOnMachineFunction() local
140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
DHexagonISelDAGToDAG.h32 const HexagonRegisterInfo *HRI; variable
37 HRI(nullptr) {} in HexagonDAGToDAGISel()
43 HRI = HST->getRegisterInfo(); in runOnMachineFunction()
DHexagonConstExtenders.cpp382 const HexagonRegisterInfo *HRI = nullptr; member
444 : Rs(R), HRI(I) {} in PrintRegister()
446 const HexagonRegisterInfo &HRI; member
452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
460 : Ex(E), HRI(I) {} in PrintExpr()
462 const HexagonRegisterInfo &HRI; member
469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); in operator <<()
478 : ExtI(EI), HRI(I) {} in PrintInit()
480 const HexagonRegisterInfo &HRI; member
486 << PrintExpr(P.ExtI.second, P.HRI) << ']'; in operator <<()
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DHexagonGenInsert.cpp569 const HexagonRegisterInfo *HRI = nullptr; member in __anon96b5abf00511::HexagonGenInsert
589 dbgs() << " " << printReg(I->first, HRI) << ":\n"; in dump_map()
592 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " in dump_map()
593 << PrintRegSet(LL[i].second, HRI) << '\n'; in dump_map()
802 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms()
803 << " AVs: " << PrintORL(AVs, HRI) << "\n"; in findRecordInsertForms()
867 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms()
872 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
919 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms()
920 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
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DHexagonBranchRelaxation.cpp69 const HexagonRegisterInfo *HRI; member
96 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
DHexagonFrameLowering.h123 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
125 const HexagonRegisterInfo &HRI) const;
DHexagonRDFOpt.cpp295 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() local
303 DataFlowGraph G(MF, HII, HRI, *MDT, MDF, TOI); in runOnMachineFunction()
DHexagonOptAddrMode.cpp84 const HexagonRegisterInfo *HRI = nullptr; member in __anon65113ab40111::HexagonOptAddrMode
345 return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); in isValidOffset()
787 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
792 DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI); in runOnMachineFunction()
DHexagonVLIWPacketizer.h74 const HexagonRegisterInfo *HRI; variable
DHexagonBitTracker.cpp95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in mask() local
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in mask()
136 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in composeWithSubRegIndex() local
137 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in composeWithSubRegIndex()
138 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi)); in composeWithSubRegIndex()
DHexagonISelLowering.cpp461 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall() local
463 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT); in LowerCall()
527 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in LowerCall()
598 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv); in LowerCall()
666 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM() local
667 unsigned LR = HRI.getRARegister(); in LowerINLINEASM()
1174 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR() local
1194 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1200 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR() local
1208 HRI.getFrameRegister(), VT); in LowerFRAMEADDR()
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DHexagonAsmPrinter.cpp270 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in HexagonProcessInstruction() local
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
DHexagonConstPropagation.cpp1894 const HexagonRegisterInfo &HRI; member in __anon034c86ec0611::HexagonConstEvaluator
1927 HRI(*Fn.getSubtarget<HexagonSubtarget>().getRegisterInfo()) { in HexagonConstEvaluator()
1960 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
2816 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg) in rewriteHexConstDefs()
DHexagonPatternsHVX.td70 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);