1 /*-
2 * Copyright (c) 2009 Yahoo! Inc.
3 * Copyright (c) 2011-2015 LSI Corp.
4 * Copyright (c) 2013-2016 Avago Technologies
5 * Copyright 2000-2020 Broadcom Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
30 *
31 * $FreeBSD: stable/12/sys/dev/mpr/mprvar.h 373239 2023-10-05 20:37:12Z asomers $
32 */
33
34 #ifndef _MPRVAR_H
35 #define _MPRVAR_H
36
37 #define MPR_DRIVER_VERSION "23.00.00.00-fbsd"
38
39 #define MPR_DB_MAX_WAIT 2500
40
41 #define MPR_REQ_FRAMES 2048
42 #define MPR_PRI_REQ_FRAMES 128
43 #define MPR_EVT_REPLY_FRAMES 32
44 #define MPR_REPLY_FRAMES MPR_REQ_FRAMES
45 #define MPR_CHAIN_FRAMES 16384
46 #define MPR_MAXIO_PAGES (-1)
47 #define MPR_SENSE_LEN SSD_FULL_SIZE
48 #define MPR_MSI_MAX 1
49 #define MPR_MSIX_MAX 96
50 #define MPR_SGE64_SIZE 12
51 #define MPR_SGE32_SIZE 8
52 #define MPR_SGC_SIZE 8
53 #define MPR_DEFAULT_CHAIN_SEG_SIZE 8
54 #define MPR_MAX_CHAIN_ELEMENT_SIZE 16
55
56 /*
57 * PCIe NVMe Specific defines
58 */
59 //SLM-for now just use the same value as a SAS disk
60 #define NVME_QDEPTH MPR_REQ_FRAMES
61 #define PRP_ENTRY_SIZE 8
62 #define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */
63 #define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */
64 #define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */
65 #define HOST_PAGE_SIZE_4K 12
66
67 #define MPR_FUNCTRACE(sc) \
68 mpr_dprint((sc), MPR_TRACE, "%s\n", __func__)
69
70 #define CAN_SLEEP 1
71 #define NO_SLEEP 0
72
73 #define MPR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */
74 #define MPR_ATA_ID_TIMEOUT 5 /* 5 second timeout for SATA ID cmd */
75 #define MPR_MISSING_CHECK_DELAY 10 /* 10 seconds between missing check */
76
77 #define IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED 0x2810
78
79 #define MPR_SCSI_RI_INVALID_FRAME (0x00000002)
80
81 #define DEFAULT_SPINUP_WAIT 3 /* seconds to wait for spinup */
82
83 #include <sys/endian.h>
84
85 /*
86 * host mapping related macro definitions
87 */
88 #define MPR_MAPTABLE_BAD_IDX 0xFFFFFFFF
89 #define MPR_DPM_BAD_IDX 0xFFFF
90 #define MPR_ENCTABLE_BAD_IDX 0xFF
91 #define MPR_MAX_MISSING_COUNT 0x0F
92 #define MPR_DEV_RESERVED 0x20000000
93 #define MPR_MAP_IN_USE 0x10000000
94 #define MPR_MAP_BAD_ID 0xFFFFFFFF
95
96 typedef uint8_t u8;
97 typedef uint16_t u16;
98 typedef uint32_t u32;
99 typedef uint64_t u64;
100
101 typedef struct _MPI2_CONFIG_PAGE_MAN_11
102 {
103 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
104 U8 FlashTime; /* 0x04 */
105 U8 NVTime; /* 0x05 */
106 U16 Flag; /* 0x06 */
107 U8 RFIoTimeout; /* 0x08 */
108 U8 EEDPTagMode; /* 0x09 */
109 U8 AWTValue; /* 0x0A */
110 U8 Reserve1; /* 0x0B */
111 U8 MaxCmdFrames; /* 0x0C */
112 U8 Reserve2; /* 0x0D */
113 U16 AddlFlags; /* 0x0E */
114 U32 SysRefClk; /* 0x10 */
115 U64 Reserve3[3]; /* 0x14 */
116 U16 AddlFlags2; /* 0x2C */
117 U8 AddlFlags3; /* 0x2E */
118 U8 Reserve4; /* 0x2F */
119 U64 opDebugEnable; /* 0x30 */
120 U64 PlDebugEnable; /* 0x38 */
121 U64 IrDebugEnable; /* 0x40 */
122 U32 BoardPowerRequirement; /* 0x48 */
123 U8 NVMeAbortTO; /* 0x4C */
124 U8 Reserve5; /* 0x4D */
125 U16 Reserve6; /* 0x4E */
126 U32 Reserve7[3]; /* 0x50 */
127 } MPI2_CONFIG_PAGE_MAN_11,
128 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_11,
129 Mpi2ManufacturingPage11_t, MPI2_POINTER pMpi2ManufacturingPage11_t;
130
131 #define MPI2_MAN_PG11_ADDLFLAGS2_CUSTOM_TM_HANDLING_MASK (0x0010)
132
133 /**
134 * struct dev_mapping_table - device mapping information
135 * @physical_id: SAS address for drives or WWID for RAID volumes
136 * @device_info: bitfield provides detailed info about the device
137 * @phy_bits: bitfields indicating controller phys
138 * @dpm_entry_num: index of this device in device persistent map table
139 * @dev_handle: device handle for the device pointed by this entry
140 * @id: target id
141 * @missing_count: number of times the device not detected by driver
142 * @hide_flag: Hide this physical disk/not (foreign configuration)
143 * @init_complete: Whether the start of the day checks completed or not
144 * @TLR_bits: Turn TLR support on or off
145 */
146 struct dev_mapping_table {
147 u64 physical_id;
148 u32 device_info;
149 u32 phy_bits;
150 u16 dpm_entry_num;
151 u16 dev_handle;
152 u16 reserved1;
153 u16 id;
154 u8 missing_count;
155 u8 init_complete;
156 u8 TLR_bits;
157 u8 reserved2;
158 };
159
160 /**
161 * struct enc_mapping_table - mapping information about an enclosure
162 * @enclosure_id: Logical ID of this enclosure
163 * @start_index: index to the entry in dev_mapping_table
164 * @phy_bits: bitfields indicating controller phys
165 * @dpm_entry_num: index of this enclosure in device persistent map table
166 * @enc_handle: device handle for the enclosure pointed by this entry
167 * @num_slots: number of slots in the enclosure
168 * @start_slot: Starting slot id
169 * @missing_count: number of times the device not detected by driver
170 * @removal_flag: used to mark the device for removal
171 * @skip_search: used as a flag to include/exclude enclosure for search
172 * @init_complete: Whether the start of the day checks completed or not
173 */
174 struct enc_mapping_table {
175 u64 enclosure_id;
176 u32 start_index;
177 u32 phy_bits;
178 u16 dpm_entry_num;
179 u16 enc_handle;
180 u16 num_slots;
181 u16 start_slot;
182 u8 missing_count;
183 u8 removal_flag;
184 u8 skip_search;
185 u8 init_complete;
186 };
187
188 /**
189 * struct map_removal_table - entries to be removed from mapping table
190 * @dpm_entry_num: index of this device in device persistent map table
191 * @dev_handle: device handle for the device pointed by this entry
192 */
193 struct map_removal_table{
194 u16 dpm_entry_num;
195 u16 dev_handle;
196 };
197
198 typedef struct mpr_fw_diagnostic_buffer {
199 size_t size;
200 uint8_t extended_type;
201 uint8_t buffer_type;
202 uint8_t force_release;
203 uint32_t product_specific[23];
204 uint8_t immediate;
205 uint8_t enabled;
206 uint8_t valid_data;
207 uint8_t owned_by_firmware;
208 uint32_t unique_id;
209 } mpr_fw_diagnostic_buffer_t;
210
211 struct mpr_softc;
212 struct mpr_command;
213 struct mprsas_softc;
214 union ccb;
215 struct mprsas_target;
216 struct mpr_column_map;
217
218 MALLOC_DECLARE(M_MPR);
219
220 typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t,
221 MPI2_EVENT_NOTIFICATION_REPLY *reply);
222 typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm);
223
224 struct mpr_chain {
225 TAILQ_ENTRY(mpr_chain) chain_link;
226 void *chain;
227 uint64_t chain_busaddr;
228 };
229
230 struct mpr_prp_page {
231 TAILQ_ENTRY(mpr_prp_page) prp_page_link;
232 uint64_t *prp_page;
233 uint64_t prp_page_busaddr;
234 };
235
236 /*
237 * This needs to be at least 2 to support SMP passthrough.
238 */
239 #define MPR_IOVEC_COUNT 2
240
241 struct mpr_command {
242 TAILQ_ENTRY(mpr_command) cm_link;
243 TAILQ_ENTRY(mpr_command) cm_recovery;
244 struct mpr_softc *cm_sc;
245 union ccb *cm_ccb;
246 void *cm_data;
247 u_int cm_length;
248 u_int cm_out_len;
249 struct uio cm_uio;
250 struct iovec cm_iovec[MPR_IOVEC_COUNT];
251 u_int cm_max_segs;
252 u_int cm_sglsize;
253 void *cm_sge;
254 uint8_t *cm_req;
255 uint8_t *cm_reply;
256 uint32_t cm_reply_data;
257 mpr_command_callback_t *cm_complete;
258 void *cm_complete_data;
259 struct mprsas_target *cm_targ;
260 MPI2_REQUEST_DESCRIPTOR_UNION cm_desc;
261 u_int cm_lun;
262 u_int cm_flags;
263 #define MPR_CM_FLAGS_POLLED (1 << 0)
264 #define MPR_CM_FLAGS_COMPLETE (1 << 1)
265 #define MPR_CM_FLAGS_SGE_SIMPLE (1 << 2)
266 #define MPR_CM_FLAGS_DATAOUT (1 << 3)
267 #define MPR_CM_FLAGS_DATAIN (1 << 4)
268 #define MPR_CM_FLAGS_WAKEUP (1 << 5)
269 #define MPR_CM_FLAGS_USE_UIO (1 << 6)
270 #define MPR_CM_FLAGS_SMP_PASS (1 << 7)
271 #define MPR_CM_FLAGS_CHAIN_FAILED (1 << 8)
272 #define MPR_CM_FLAGS_ERROR_MASK MPR_CM_FLAGS_CHAIN_FAILED
273 #define MPR_CM_FLAGS_USE_CCB (1 << 9)
274 #define MPR_CM_FLAGS_SATA_ID_TIMEOUT (1 << 10)
275 #define MPR_CM_FLAGS_ON_RECOVERY (1 << 12)
276 #define MPR_CM_FLAGS_TIMEDOUT (1 << 13)
277 u_int cm_state;
278 #define MPR_CM_STATE_FREE 0
279 #define MPR_CM_STATE_BUSY 1
280 #define MPR_CM_STATE_INQUEUE 2
281 bus_dmamap_t cm_dmamap;
282 struct scsi_sense_data *cm_sense;
283 uint64_t *nvme_error_response;
284 TAILQ_HEAD(, mpr_chain) cm_chain_list;
285 TAILQ_HEAD(, mpr_prp_page) cm_prp_page_list;
286 uint32_t cm_req_busaddr;
287 bus_addr_t cm_sense_busaddr;
288 struct callout cm_callout;
289 mpr_command_callback_t *cm_timeout_handler;
290 };
291
292 struct mpr_column_map {
293 uint16_t dev_handle;
294 uint8_t phys_disk_num;
295 };
296
297 struct mpr_event_handle {
298 TAILQ_ENTRY(mpr_event_handle) eh_list;
299 mpr_evt_callback_t *callback;
300 void *data;
301 uint8_t mask[16];
302 };
303
304 struct mpr_busdma_context {
305 int completed;
306 int abandoned;
307 int error;
308 bus_addr_t *addr;
309 struct mpr_softc *softc;
310 bus_dmamap_t buffer_dmamap;
311 bus_dma_tag_t buffer_dmat;
312 };
313
314 struct mpr_queue {
315 struct mpr_softc *sc;
316 int qnum;
317 MPI2_REPLY_DESCRIPTORS_UNION *post_queue;
318 int replypostindex;
319 #ifdef notyet
320 ck_ring_buffer_t *ringmem;
321 ck_ring_buffer_t *chainmem;
322 ck_ring_t req_ring;
323 ck_ring_t chain_ring;
324 #endif
325 bus_dma_tag_t buffer_dmat;
326 int io_cmds_highwater;
327 int chain_free_lowwater;
328 int chain_alloc_fail;
329 struct resource *irq;
330 void *intrhand;
331 int irq_rid;
332 };
333
334 struct mpr_softc {
335 device_t mpr_dev;
336 struct cdev *mpr_cdev;
337 u_int mpr_flags;
338 #define MPR_FLAGS_INTX (1 << 0)
339 #define MPR_FLAGS_MSI (1 << 1)
340 #define MPR_FLAGS_BUSY (1 << 2)
341 #define MPR_FLAGS_SHUTDOWN (1 << 3)
342 #define MPR_FLAGS_DIAGRESET (1 << 4)
343 #define MPR_FLAGS_ATTACH_DONE (1 << 5)
344 #define MPR_FLAGS_GEN35_IOC (1 << 6)
345 #define MPR_FLAGS_REALLOCATED (1 << 7)
346 #define MPR_FLAGS_SEA_IOC (1 << 8)
347 u_int mpr_debug;
348 int msi_msgs;
349 u_int reqframesz;
350 u_int replyframesz;
351 u_int atomic_desc_capable;
352 int tm_cmds_active;
353 int io_cmds_active;
354 int io_cmds_highwater;
355 int chain_free;
356 int max_chains;
357 int max_io_pages;
358 u_int maxio;
359 int chain_free_lowwater;
360 uint32_t chain_frame_size;
361 int prp_buffer_size;
362 int prp_pages_free;
363 int prp_pages_free_lowwater;
364 u_int enable_ssu;
365 int spinup_wait_time;
366 int use_phynum;
367 uint64_t chain_alloc_fail;
368 uint64_t prp_page_alloc_fail;
369 struct sysctl_ctx_list sysctl_ctx;
370 struct sysctl_oid *sysctl_tree;
371 char fw_version[16];
372 char msg_version[8];
373 struct mpr_command *commands;
374 struct mpr_chain *chains;
375 struct mpr_prp_page *prps;
376 struct callout periodic;
377 struct callout device_check_callout;
378 struct mpr_queue *queues;
379
380 struct mprsas_softc *sassc;
381 TAILQ_HEAD(, mpr_command) req_list;
382 TAILQ_HEAD(, mpr_command) high_priority_req_list;
383 TAILQ_HEAD(, mpr_chain) chain_list;
384 TAILQ_HEAD(, mpr_prp_page) prp_page_list;
385 TAILQ_HEAD(, mpr_command) tm_list;
386 int replypostindex;
387 int replyfreeindex;
388
389 struct resource *mpr_regs_resource;
390 bus_space_handle_t mpr_bhandle;
391 bus_space_tag_t mpr_btag;
392 int mpr_regs_rid;
393
394 bus_dma_tag_t mpr_parent_dmat;
395 bus_dma_tag_t buffer_dmat;
396
397 MPI2_IOC_FACTS_REPLY *facts;
398 int num_reqs;
399 int num_prireqs;
400 int num_replies;
401 int num_chains;
402 int fqdepth; /* Free queue */
403 int pqdepth; /* Post queue */
404
405 uint8_t event_mask[16];
406 TAILQ_HEAD(, mpr_event_handle) event_list;
407 struct mpr_event_handle *mpr_log_eh;
408
409 struct mtx mpr_mtx;
410 struct intr_config_hook mpr_ich;
411
412 uint8_t *req_frames;
413 bus_addr_t req_busaddr;
414 bus_dma_tag_t req_dmat;
415 bus_dmamap_t req_map;
416
417 uint8_t *reply_frames;
418 bus_addr_t reply_busaddr;
419 bus_dma_tag_t reply_dmat;
420 bus_dmamap_t reply_map;
421
422 struct scsi_sense_data *sense_frames;
423 bus_addr_t sense_busaddr;
424 bus_dma_tag_t sense_dmat;
425 bus_dmamap_t sense_map;
426
427 uint8_t *chain_frames;
428 bus_dma_tag_t chain_dmat;
429 bus_dmamap_t chain_map;
430
431 uint8_t *prp_pages;
432 bus_addr_t prp_page_busaddr;
433 bus_dma_tag_t prp_page_dmat;
434 bus_dmamap_t prp_page_map;
435
436 MPI2_REPLY_DESCRIPTORS_UNION *post_queue;
437 bus_addr_t post_busaddr;
438 uint32_t *free_queue;
439 bus_addr_t free_busaddr;
440 bus_dma_tag_t queues_dmat;
441 bus_dmamap_t queues_map;
442
443 uint8_t *fw_diag_buffer;
444 bus_addr_t fw_diag_busaddr;
445 bus_dma_tag_t fw_diag_dmat;
446 bus_dmamap_t fw_diag_map;
447
448 uint8_t ir_firmware;
449
450 /* static config pages */
451 Mpi2IOCPage8_t ioc_pg8;
452 Mpi2IOUnitPage8_t iounit_pg8;
453
454 /* host mapping support */
455 struct dev_mapping_table *mapping_table;
456 struct enc_mapping_table *enclosure_table;
457 struct map_removal_table *removal_table;
458 uint8_t *dpm_entry_used;
459 uint8_t *dpm_flush_entry;
460 Mpi2DriverMappingPage0_t *dpm_pg0;
461 uint16_t max_devices;
462 uint16_t max_enclosures;
463 uint16_t max_expanders;
464 uint8_t max_volumes;
465 uint8_t num_enc_table_entries;
466 uint8_t num_rsvd_entries;
467 uint16_t max_dpm_entries;
468 uint8_t is_dpm_enable;
469 uint8_t track_mapping_events;
470 uint32_t pending_map_events;
471
472 /* FW diag Buffer List */
473 mpr_fw_diagnostic_buffer_t
474 fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
475
476 /* Event Recording IOCTL support */
477 uint32_t events_to_record[4];
478 mpr_event_entry_t recorded_events[MPR_EVENT_QUEUE_SIZE];
479 uint8_t event_index;
480 uint32_t event_number;
481
482 /* EEDP and TLR support */
483 uint8_t eedp_enabled;
484 uint8_t control_TLR;
485
486 /* Shutdown Event Handler */
487 eventhandler_tag shutdown_eh;
488
489 /* To track topo events during reset */
490 #define MPR_DIAG_RESET_TIMEOUT 300000
491 uint8_t wait_for_port_enable;
492 uint8_t port_enable_complete;
493 uint8_t msleep_fake_chan;
494
495 /* StartStopUnit command handling at shutdown */
496 uint32_t SSU_refcount;
497 uint8_t SSU_started;
498
499 /* Configuration tunables */
500 u_int disable_msix;
501 u_int disable_msi;
502 u_int max_msix;
503 u_int max_reqframes;
504 u_int max_prireqframes;
505 u_int max_replyframes;
506 u_int max_evtframes;
507 char exclude_ids[80];
508
509 struct timeval lastfail;
510 uint8_t custom_nvme_tm_handling;
511 uint8_t nvme_abort_timeout;
512 };
513
514 struct mpr_config_params {
515 MPI2_CONFIG_EXT_PAGE_HEADER_UNION hdr;
516 u_int action;
517 u_int page_address; /* Attributes, not a phys address */
518 u_int status;
519 void *buffer;
520 u_int length;
521 int timeout;
522 void (*callback)(struct mpr_softc *, struct mpr_config_params *);
523 void *cbdata;
524 };
525
526 struct scsi_read_capacity_eedp
527 {
528 uint8_t addr[8];
529 uint8_t length[4];
530 uint8_t protect;
531 };
532
533 static __inline uint32_t
mpr_regread(struct mpr_softc * sc,uint32_t offset)534 mpr_regread(struct mpr_softc *sc, uint32_t offset)
535 {
536 uint32_t ret_val, i = 0;
537 do {
538 ret_val =
539 bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset);
540 } while((sc->mpr_flags & MPR_FLAGS_SEA_IOC) &&
541 (ret_val == 0) && (++i < 3));
542
543 return ret_val;
544 }
545
546 static __inline void
mpr_regwrite(struct mpr_softc * sc,uint32_t offset,uint32_t val)547 mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val)
548 {
549 bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val);
550 }
551
552 /* free_queue must have Little Endian address
553 * TODO- cm_reply_data is unwanted. We can remove it.
554 * */
555 static __inline void
mpr_free_reply(struct mpr_softc * sc,uint32_t busaddr)556 mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr)
557 {
558 if (++sc->replyfreeindex >= sc->fqdepth)
559 sc->replyfreeindex = 0;
560 sc->free_queue[sc->replyfreeindex] = htole32(busaddr);
561 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
562 }
563
564 static __inline struct mpr_chain *
mpr_alloc_chain(struct mpr_softc * sc)565 mpr_alloc_chain(struct mpr_softc *sc)
566 {
567 struct mpr_chain *chain;
568
569 if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) {
570 TAILQ_REMOVE(&sc->chain_list, chain, chain_link);
571 sc->chain_free--;
572 if (sc->chain_free < sc->chain_free_lowwater)
573 sc->chain_free_lowwater = sc->chain_free;
574 } else
575 sc->chain_alloc_fail++;
576 return (chain);
577 }
578
579 static __inline void
mpr_free_chain(struct mpr_softc * sc,struct mpr_chain * chain)580 mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain)
581 {
582 #if 0
583 bzero(chain->chain, 128);
584 #endif
585 sc->chain_free++;
586 TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link);
587 }
588
589 static __inline struct mpr_prp_page *
mpr_alloc_prp_page(struct mpr_softc * sc)590 mpr_alloc_prp_page(struct mpr_softc *sc)
591 {
592 struct mpr_prp_page *prp_page;
593
594 if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) {
595 TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link);
596 sc->prp_pages_free--;
597 if (sc->prp_pages_free < sc->prp_pages_free_lowwater)
598 sc->prp_pages_free_lowwater = sc->prp_pages_free;
599 } else
600 sc->prp_page_alloc_fail++;
601 return (prp_page);
602 }
603
604 static __inline void
mpr_free_prp_page(struct mpr_softc * sc,struct mpr_prp_page * prp_page)605 mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page)
606 {
607 sc->prp_pages_free++;
608 TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link);
609 }
610
611 static __inline void
mpr_free_command(struct mpr_softc * sc,struct mpr_command * cm)612 mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm)
613 {
614 struct mpr_chain *chain, *chain_temp;
615 struct mpr_prp_page *prp_page, *prp_page_temp;
616
617 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n"));
618
619 if (cm->cm_reply != NULL)
620 mpr_free_reply(sc, cm->cm_reply_data);
621 cm->cm_reply = NULL;
622 cm->cm_flags = 0;
623 cm->cm_complete = NULL;
624 cm->cm_complete_data = NULL;
625 cm->cm_ccb = NULL;
626 cm->cm_targ = NULL;
627 cm->cm_max_segs = 0;
628 cm->cm_lun = 0;
629 cm->cm_state = MPR_CM_STATE_FREE;
630 cm->cm_data = NULL;
631 cm->cm_length = 0;
632 cm->cm_out_len = 0;
633 cm->cm_sglsize = 0;
634 cm->cm_sge = NULL;
635
636 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
637 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
638 mpr_free_chain(sc, chain);
639 }
640 TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link,
641 prp_page_temp) {
642 TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link);
643 mpr_free_prp_page(sc, prp_page);
644 }
645 TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link);
646 }
647
648 static __inline struct mpr_command *
mpr_alloc_command(struct mpr_softc * sc)649 mpr_alloc_command(struct mpr_softc *sc)
650 {
651 struct mpr_command *cm;
652
653 cm = TAILQ_FIRST(&sc->req_list);
654 if (cm == NULL)
655 return (NULL);
656
657 KASSERT(cm->cm_state == MPR_CM_STATE_FREE,
658 ("mpr: Allocating busy command\n"));
659
660 TAILQ_REMOVE(&sc->req_list, cm, cm_link);
661 cm->cm_state = MPR_CM_STATE_BUSY;
662 cm->cm_timeout_handler = NULL;
663 return (cm);
664 }
665
666 static __inline void
mpr_free_high_priority_command(struct mpr_softc * sc,struct mpr_command * cm)667 mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm)
668 {
669 struct mpr_chain *chain, *chain_temp;
670
671 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n"));
672
673 if (cm->cm_reply != NULL)
674 mpr_free_reply(sc, cm->cm_reply_data);
675 cm->cm_reply = NULL;
676 cm->cm_flags = 0;
677 cm->cm_complete = NULL;
678 cm->cm_complete_data = NULL;
679 cm->cm_ccb = NULL;
680 cm->cm_targ = NULL;
681 cm->cm_lun = 0;
682 cm->cm_state = MPR_CM_STATE_FREE;
683 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
684 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
685 mpr_free_chain(sc, chain);
686 }
687 TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link);
688 }
689
690 static __inline struct mpr_command *
mpr_alloc_high_priority_command(struct mpr_softc * sc)691 mpr_alloc_high_priority_command(struct mpr_softc *sc)
692 {
693 struct mpr_command *cm;
694
695 cm = TAILQ_FIRST(&sc->high_priority_req_list);
696 if (cm == NULL)
697 return (NULL);
698
699 KASSERT(cm->cm_state == MPR_CM_STATE_FREE,
700 ("mpr: Allocating busy command\n"));
701
702 TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link);
703 cm->cm_state = MPR_CM_STATE_BUSY;
704 cm->cm_timeout_handler = NULL;
705 cm->cm_desc.HighPriority.RequestFlags =
706 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
707 return (cm);
708 }
709
710 static __inline void
mpr_lock(struct mpr_softc * sc)711 mpr_lock(struct mpr_softc *sc)
712 {
713 mtx_lock(&sc->mpr_mtx);
714 }
715
716 static __inline void
mpr_unlock(struct mpr_softc * sc)717 mpr_unlock(struct mpr_softc *sc)
718 {
719 mtx_unlock(&sc->mpr_mtx);
720 }
721
722 #define MPR_INFO (1 << 0) /* Basic info */
723 #define MPR_FAULT (1 << 1) /* Hardware faults */
724 #define MPR_EVENT (1 << 2) /* Event data from the controller */
725 #define MPR_LOG (1 << 3) /* Log data from the controller */
726 #define MPR_RECOVERY (1 << 4) /* Command error recovery tracing */
727 #define MPR_ERROR (1 << 5) /* Parameter errors, programming bugs */
728 #define MPR_INIT (1 << 6) /* Things related to system init */
729 #define MPR_XINFO (1 << 7) /* More detailed/noisy info */
730 #define MPR_USER (1 << 8) /* Trace user-generated commands */
731 #define MPR_MAPPING (1 << 9) /* Trace device mappings */
732 #define MPR_TRACE (1 << 10) /* Function-by-function trace */
733
734 #define MPR_SSU_DISABLE_SSD_DISABLE_HDD 0
735 #define MPR_SSU_ENABLE_SSD_DISABLE_HDD 1
736 #define MPR_SSU_DISABLE_SSD_ENABLE_HDD 2
737 #define MPR_SSU_ENABLE_SSD_ENABLE_HDD 3
738
739 #define mpr_printf(sc, args...) \
740 device_printf((sc)->mpr_dev, ##args)
741
742 #define mpr_print_field(sc, msg, args...) \
743 printf("\t" msg, ##args)
744
745 #define mpr_vprintf(sc, args...) \
746 do { \
747 if (bootverbose) \
748 mpr_printf(sc, ##args); \
749 } while (0)
750
751 #define mpr_dprint(sc, level, msg, args...) \
752 do { \
753 if ((sc)->mpr_debug & (level)) \
754 device_printf((sc)->mpr_dev, msg, ##args); \
755 } while (0)
756
757 #define MPR_PRINTFIELD_START(sc, tag...) \
758 mpr_printf((sc), ##tag); \
759 mpr_print_field((sc), ":\n")
760 #define MPR_PRINTFIELD_END(sc, tag) \
761 mpr_printf((sc), tag "\n")
762 #define MPR_PRINTFIELD(sc, facts, attr, fmt) \
763 mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr)
764 #define MPR_PRINTFIELD_16(sc, facts, attr, fmt) \
765 mpr_print_field((sc), #attr ": " #fmt "\n", le16toh((facts)->attr))
766 #define MPR_PRINTFIELD_32(sc, facts, attr, fmt) \
767 mpr_print_field((sc), #attr ": " #fmt "\n", le32toh((facts)->attr))
768
769 static __inline void
mpr_from_u64(uint64_t data,U64 * mpr)770 mpr_from_u64(uint64_t data, U64 *mpr)
771 {
772 (mpr)->High = htole32((uint32_t)((data) >> 32));
773 (mpr)->Low = htole32((uint32_t)((data) & 0xffffffff));
774 }
775
776 static __inline uint64_t
mpr_to_u64(U64 * data)777 mpr_to_u64(U64 *data)
778 {
779 return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low));
780 }
781
782 static __inline void
mpr_mask_intr(struct mpr_softc * sc)783 mpr_mask_intr(struct mpr_softc *sc)
784 {
785 uint32_t mask;
786
787 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
788 mask |= MPI2_HIM_REPLY_INT_MASK;
789 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
790 }
791
792 static __inline void
mpr_unmask_intr(struct mpr_softc * sc)793 mpr_unmask_intr(struct mpr_softc *sc)
794 {
795 uint32_t mask;
796
797 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
798 mask &= ~MPI2_HIM_REPLY_INT_MASK;
799 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
800 }
801
802 int mpr_pci_setup_interrupts(struct mpr_softc *sc);
803 void mpr_pci_free_interrupts(struct mpr_softc *sc);
804 int mpr_pci_restore(struct mpr_softc *sc);
805
806 void mpr_get_tunables(struct mpr_softc *sc);
807 int mpr_attach(struct mpr_softc *sc);
808 int mpr_free(struct mpr_softc *sc);
809 void mpr_intr(void *);
810 void mpr_intr_msi(void *);
811 void mpr_intr_locked(void *);
812 int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *,
813 void *, struct mpr_event_handle **);
814 int mpr_restart(struct mpr_softc *);
815 int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *);
816 int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *);
817 void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
818 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
819 uint32_t data_in_sz, uint32_t data_out_sz);
820 int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int);
821 int mpr_push_ieee_sge(struct mpr_command *, void *, int);
822 int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int);
823 int mpr_attach_sas(struct mpr_softc *sc);
824 int mpr_detach_sas(struct mpr_softc *sc);
825 int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *);
826 int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *);
827 void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int );
828 void mpr_memaddr_wait_cb(void *, bus_dma_segment_t *, int , int );
829 void mpr_init_sge(struct mpr_command *cm, void *req, void *sge);
830 int mpr_attach_user(struct mpr_softc *);
831 void mpr_detach_user(struct mpr_softc *);
832 void mprsas_record_event(struct mpr_softc *sc,
833 MPI2_EVENT_NOTIFICATION_REPLY *event_reply);
834
835 int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm);
836 int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout,
837 int sleep_flag);
838 int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm);
839
840 int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t
841 *mpi_reply, Mpi2BiosPage3_t *config_page);
842 int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
843 *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address);
844 int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *,
845 Mpi2IOCPage8_t *);
846 int mpr_config_get_iounit_pg8(struct mpr_softc *sc,
847 Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page);
848 int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
849 Mpi2SasDevicePage0_t *, u32 , u16 );
850 int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
851 *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle);
852 int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t
853 *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle);
854 int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
855 Mpi2DriverMappingPage0_t *, u16 );
856 int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc,
857 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,
858 u16 handle);
859 int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle,
860 u64 *wwid);
861 int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc,
862 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page,
863 u32 page_address);
864 int mpr_config_get_man_pg11(struct mpr_softc *sc, Mpi2ConfigReply_t *mpi_reply,
865 Mpi2ManufacturingPage11_t *config_page);
866 void mprsas_ir_shutdown(struct mpr_softc *sc, int howto);
867
868 int mpr_reinit(struct mpr_softc *sc);
869 void mprsas_handle_reinit(struct mpr_softc *sc);
870
871 void mpr_base_static_config_pages(struct mpr_softc *sc);
872
873 int mpr_mapping_initialize(struct mpr_softc *);
874 void mpr_mapping_topology_change_event(struct mpr_softc *,
875 Mpi2EventDataSasTopologyChangeList_t *);
876 void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc,
877 Mpi26EventDataPCIeTopologyChangeList_t *event_data);
878 void mpr_mapping_free_memory(struct mpr_softc *sc);
879 int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
880 Mpi2DriverMappingPage0_t *, u16 );
881 void mpr_mapping_exit(struct mpr_softc *);
882 void mpr_mapping_check_devices(void *);
883 int mpr_mapping_allocate_memory(struct mpr_softc *sc);
884 unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16);
885 unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc,
886 u16 handle);
887 unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid,
888 u16 volHandle);
889 unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc,
890 u16 volHandle);
891 void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *,
892 Mpi2EventDataSasEnclDevStatusChange_t *event_data);
893 void mpr_mapping_ir_config_change_event(struct mpr_softc *sc,
894 Mpi2EventDataIrConfigChangeList_t *event_data);
895
896 void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data,
897 MPI2_EVENT_NOTIFICATION_REPLY *event);
898 void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle);
899 void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle);
900 int mprsas_startup(struct mpr_softc *sc);
901 struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int,
902 uint16_t);
903 void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets);
904 struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc);
905 void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm);
906 void mprsas_release_simq_reinit(struct mprsas_softc *sassc);
907 int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm,
908 uint8_t type);
909
910 SYSCTL_DECL(_hw_mpr);
911
912 /* Compatibility shims for different OS versions */
913 #if defined(CAM_PRIORITY_XPT)
914 #define MPR_PRIORITY_XPT CAM_PRIORITY_XPT
915 #else
916 #define MPR_PRIORITY_XPT 5
917 #endif
918
919 #if __FreeBSD_version < 800107
920 // Prior to FreeBSD-8.0 scp3_flags was not defined.
921 #define spc3_flags reserved
922
923 #define SPC3_SID_PROTECT 0x01
924 #define SPC3_SID_3PC 0x08
925 #define SPC3_SID_TPGS_MASK 0x30
926 #define SPC3_SID_TPGS_IMPLICIT 0x10
927 #define SPC3_SID_TPGS_EXPLICIT 0x20
928 #define SPC3_SID_ACC 0x40
929 #define SPC3_SID_SCCS 0x80
930
931 #define CAM_PRIORITY_NORMAL CAM_PRIORITY_NONE
932 #endif
933
934 /* Definitions for SCSI unmap translation to NVMe DSM command */
935
936 /* UNMAP block descriptor structure */
937 struct unmap_blk_desc {
938 uint64_t slba;
939 uint32_t nlb;
940 uint32_t resv;
941 };
942
943 /* UNMAP command's data */
944 struct unmap_parm_list {
945 uint16_t unmap_data_len;
946 uint16_t unmap_blk_desc_data_len;
947 uint32_t resv;
948 struct unmap_blk_desc desc[0];
949 };
950
951 /* SCSI ADDITIONAL SENSE Codes */
952 #define FIXED_SENSE_DATA 0x70
953 #define SCSI_ASC_NO_SENSE 0x00
954 #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
955 #define SCSI_ASC_LUN_NOT_READY 0x04
956 #define SCSI_ASC_WARNING 0x0B
957 #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
958 #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
959 #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
960 #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
961 #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
962 #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
963 #define SCSI_ASC_ILLEGAL_COMMAND 0x20
964 #define SCSI_ASC_ILLEGAL_BLOCK 0x21
965 #define SCSI_ASC_INVALID_CDB 0x24
966 #define SCSI_ASC_INVALID_LUN 0x25
967 #define SCSI_ASC_INVALID_PARAMETER 0x26
968 #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
969 #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
970
971 /* SCSI ADDITIONAL SENSE Code Qualifiers */
972 #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
973 #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
974 #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
975 #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
976 #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
977 #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
978 #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
979 #define SCSI_ASCQ_INVALID_LUN_ID 0x09
980
981 #endif
982
983