| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 662 FSHL, enumerator
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 385 case ISD::FSHL: in LegalizeOp()
805 case ISD::FSHL: in Expand()
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| D | SelectionDAGDumper.cpp | 252 case ISD::FSHL: return "fshl"; in getOperationName()
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| D | TargetLowering.cpp | 1669 case ISD::FSHL: in SimplifyDemandedBits()
1674 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
6503 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
6509 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
6660 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
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| D | LegalizeVectorTypes.cpp | 155 case ISD::FSHL: in ScalarizeVectorResult()
1051 case ISD::FSHL: in SplitVectorResult()
3158 case ISD::FSHL: in WidenVectorResult()
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| D | DAGCombiner.cpp | 1656 case ISD::FSHL: in visit()
6883 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
6896 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
6897 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
6936 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
7023 Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7084 LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7090 RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
8988 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
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| D | LegalizeDAG.cpp | 1221 case ISD::FSHL: in LegalizeOp()
3348 case ISD::FSHL: in ExpandNode()
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| D | LegalizeIntegerTypes.cpp | 232 case ISD::FSHL: in PromoteIntegerResult()
2246 case ISD::FSHL: in ExpandIntegerResult()
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| D | SelectionDAG.cpp | 3122 case ISD::FSHL: in computeKnownBits()
3130 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3139 if (Opcode == ISD::FSHL) { in computeKnownBits()
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| D | SelectionDAGBuilder.cpp | 6457 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 38 FSHL, enumerator
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| D | X86TargetTransformInfo.cpp | 3237 { ISD::FSHL, MVT::i64, 4 } in getIntrinsicInstrCost()
3246 { ISD::FSHL, MVT::i32, 4 }, in getIntrinsicInstrCost()
3247 { ISD::FSHL, MVT::i16, 4 }, in getIntrinsicInstrCost()
3248 { ISD::FSHL, MVT::i8, 4 } in getIntrinsicInstrCost()
3259 ISD = ISD::FSHL; in getIntrinsicInstrCost()
3265 ISD = ISD::FSHL; in getIntrinsicInstrCost()
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| D | X86ISelLowering.cpp | 217 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1759 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
19692 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
19768 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
28963 unsigned FunnelOpc = (Opcode == ISD::ROTL ? ISD::FSHL : ISD::FSHR); in LowerRotate()
30466 case ISD::FSHL: in LowerOperation()
31488 NODE_NAME_CASE(FSHL) in getTargetNodeName()
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| D | X86InstrInfo.td | 143 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 290 setOperationAction(ISD::FSHL, XLenVT, Custom); in RISCVTargetLowering()
295 setOperationAction(ISD::FSHL, MVT::i32, Custom); in RISCVTargetLowering()
2183 case ISD::FSHL: in LowerOperation()
2195 unsigned Opc = Op.getOpcode() == ISD::FSHL ? RISCVISD::FSL : RISCVISD::FSR; in LowerOperation()
5162 case ISD::FSHL: in ReplaceNodeResults()
5177 N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; in ReplaceNodeResults()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 776 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1581 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1582 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 387 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 708 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
711 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
8856 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
10873 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
10972 case ISD::FSHL: in ReplaceNodeResults()
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