| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 381 FREM, enumerator
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| D | TargetLowering.h | 2490 case ISD::FREM: in isBinOp()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 697 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| D | SelectionDAGDumper.cpp | 265 case ISD::FREM: return "frem"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 114 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1255 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2260 case ISD::FREM: in PromoteFloatResult()
2625 case ISD::FREM: in SoftPromoteHalfResult()
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| D | LegalizeVectorOps.cpp | 378 case ISD::FREM: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 137 case ISD::FREM: in ScalarizeVectorResult()
1035 case ISD::FREM: in SplitVectorResult()
3046 case ISD::FREM: in WidenVectorResult()
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| D | FastISel.cpp | 1723 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| D | SelectionDAG.cpp | 4339 case ISD::FREM: in isKnownNeverNaN()
5468 case ISD::FREM: in foldConstantFPMath()
5497 case ISD::FREM: in foldConstantFPMath()
5668 case ISD::FREM: in getNode()
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| D | LegalizeDAG.cpp | 4104 case ISD::FREM: in ConvertNodeToLibcall()
4665 case ISD::FREM: in PromoteNode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 346 setOperationAction(ISD::FREM, MVT::f16, Custom); in AMDGPUTargetLowering()
347 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering()
348 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering()
512 setOperationAction(ISD::FREM, VT, Expand); in AMDGPUTargetLowering()
681 case ISD::FREM: in hasSourceMods()
1291 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| D | AMDGPUTargetTransformInfo.cpp | 658 case ISD::FREM: in getArithmeticInstrCost()
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| D | AMDGPUISelDAGToDAG.cpp | 416 case ISD::FREM: in fp16SrcZerosHighBits()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1631 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1641 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1792 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 355 setOperationAction(ISD::FREM, VT, Expand); in AArch64TargetLowering()
411 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
412 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
413 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering()
433 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
580 setOperationAction(ISD::FREM, MVT::f16, Promote); in AArch64TargetLowering()
581 setOperationAction(ISD::FREM, MVT::v4f16, Expand); in AArch64TargetLowering()
582 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering()
979 setOperationAction(ISD::FREM, MVT::v1f64, Expand); in AArch64TargetLowering()
1452 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1596 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1641 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 120 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 447 setOperationAction(ISD::FREM, MVT::f32, Expand); in MipsTargetLowering()
448 setOperationAction(ISD::FREM, MVT::f64, Expand); in MipsTargetLowering()
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| D | MipsSEISelLowering.cpp | 136 setOperationAction(ISD::FREM, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 225 setOperationAction(ISD::FREM, VT, Expand); in initSPUActions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 460 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 202 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
355 setOperationAction(ISD::FREM, VT, Expand); in addMVEVectorTypes()
827 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
1018 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1397 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1398 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1473 setOperationAction(ISD::FREM, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 300 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
375 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
380 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
799 setOperationAction(ISD::FREM, VT, Expand); in PPCTargetLowering()
1138 setOperationAction(ISD::FREM, MVT::f128, Expand); in PPCTargetLowering()
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