Searched refs:FP1 (Results 1 – 11 of 11) sorted by relevance
| /freebsd-12-stable/contrib/file/magic/Magdir/ |
| D | finger | 10 0 string FP1 libfprint fingerprint data V1
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| /freebsd-12-stable/contrib/gdb/gdb/ |
| D | dpx2-nat.c | 42 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 33 list<Register> FP_RET = [FP0, FP1];
257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>>
269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
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| D | X86RegisterInfo.td | 203 def FP1 : X86Reg<"fp1", 0>;
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| D | X86FastISel.cpp | 1240 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
3550 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && in fastLowerCall()
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| D | X86InstrCompiler.td | 450 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
470 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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| D | X86ISelLowering.cpp | 2750 VA.getLocReg() == X86::FP1) { in LowerReturn()
2800 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) { in LowerReturn()
3068 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts. in LowerCallResult()
3076 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts. in LowerCallResult()
3084 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
4719 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in IsEligibleForTailCallOptimization()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 115 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX3T110.td | 89 // FP micro-ops on ports FP0/FP1/FP2/FP3.
96 // ASIMD micro-ops on ports FP0/FP1/FP2/FP3.
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| /freebsd-12-stable/sys/dev/drm2/i915/ |
| D | i915_reg.h | 1049 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) macro
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| D | intel_display.c | 4304 I915_WRITE(FP1(pipe), fp2); in i9xx_update_pll_dividers()
4307 I915_WRITE(FP1(pipe), fp); in i9xx_update_pll_dividers()
6840 fp = I915_READ(FP1(pipe)); in intel_crtc_clock_get()
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