1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/12/sys/sparc64/pci/firereg.h 326262 2017-11-27 15:10:39Z pfg $ 29 */ 30 31 #ifndef _SPARC64_PCI_FIREREG_H_ 32 #define _SPARC64_PCI_FIREREG_H_ 33 34 #define FIRE_NINTR 3 /* 2 OFW + 1 MSIq */ 35 #define FIRE_NREG 2 36 37 #define FIRE_PCI 0 38 #define FIRE_CTRL 1 39 40 /* PCI configuration and status registers */ 41 #define FO_PCI_INT_MAP_BASE 0x01000 42 #define FO_PCI_INT_CLR_BASE 0x01400 43 #define FO_PCI_EQ_BASE_ADDR 0x10000 44 #define FO_PCI_EQ_CTRL_SET_BASE 0x11000 45 #define FO_PCI_EQ_CTRL_CLR_BASE 0x11200 46 #define FO_PCI_EQ_TL_BASE 0x11600 47 #define FO_PCI_EQ_HD_BASE 0x11800 48 #define FO_PCI_MSI_MAP_BASE 0x20000 49 #define FO_PCI_MSI_CLR_BASE 0x28000 50 #define FO_PCI_ERR_COR 0x30000 51 #define FO_PCI_ERR_NONFATAL 0x30008 52 #define FO_PCI_ERR_FATAL 0x30010 53 #define FO_PCI_PM_PME 0x30018 54 #define FO_PCI_PME_TO_ACK 0x30020 55 #define FO_PCI_IMU_INT_EN 0x31008 56 #define FO_PCI_IMU_INT_STAT 0x31010 57 #define FO_PCI_IMU_ERR_STAT_CLR 0x31018 58 #define FO_PCI_IMU_RDS_ERR_LOG 0x31028 59 #define FO_PCI_IMU_SCS_ERR_LOG 0x31030 60 #define FO_PCI_IMU_EQS_ERR_LOG 0x31038 61 #define FO_PCI_DMC_CORE_BLOCK_INT_EN 0x31800 62 #define FO_PCI_DMC_CORE_BLOCK_ERR_STAT 0x31808 63 #define FO_PCI_MULTI_CORE_ERR_STAT 0x31810 64 #define FO_PCI_MSI_32_BIT_ADDR 0x34000 65 #define FO_PCI_MSI_64_BIT_ADDR 0x34008 66 #define FO_PCI_MMU 0x40000 67 #define FO_PCI_MMU_INT_EN 0x41008 68 #define FO_PCI_MMU_INT_STAT 0x41010 69 #define FO_PCI_MMU_ERR_STAT_CLR 0x41018 70 #define FO_PCI_MMU_TRANS_FAULT_ADDR 0x41028 71 #define FO_PCI_MMU_TRANS_FAULT_STAT 0x41030 72 #define FO_PCI_ILU_INT_EN 0x51008 73 #define FO_PCI_ILU_INT_STAT 0x51010 74 #define FO_PCI_ILU_ERR_STAT_CLR 0x51018 75 #define FO_PCI_DMC_DBG_SEL_PORTA 0x53000 76 #define FO_PCI_DMC_DBG_SEL_PORTB 0x53008 77 #define FO_PCI_PEC_CORE_BLOCK_INT_EN 0x51800 78 #define FO_PCI_PEC_CORE_BLOCK_INT_STAT 0x51808 79 #define FO_PCI_TLU_CTRL 0x80000 80 #define FO_PCI_TLU_OEVENT_INT_EN 0x81008 81 #define FO_PCI_TLU_OEVENT_INT_STAT 0x81010 82 #define FO_PCI_TLU_OEVENT_STAT_CLR 0x81018 83 #define FO_PCI_TLU_RX_OEVENT_HDR1_LOG 0x81028 84 #define FO_PCI_TLU_RX_OEVENT_HDR2_LOG 0x81030 85 #define FO_PCI_TLU_TX_OEVENT_HDR1_LOG 0x81038 86 #define FO_PCI_TLU_TX_OEVENT_HDR2_LOG 0x81040 87 #define FO_PCI_TLU_DEV_CTRL 0x90008 88 #define FO_PCI_TLU_LNK_CTRL 0x90020 89 #define FO_PCI_TLU_LNK_STAT 0x90028 90 #define FO_PCI_TLU_UERR_INT_EN 0x91008 91 #define FO_PCI_TLU_UERR_INT_STAT 0x91010 92 #define FO_PCI_TLU_UERR_STAT_CLR 0x91018 93 #define FO_PCI_TLU_RX_UERR_HDR1_LOG 0x91028 94 #define FO_PCI_TLU_RX_UERR_HDR2_LOG 0x91030 95 #define FO_PCI_TLU_TX_UERR_HDR1_LOG 0x91038 96 #define FO_PCI_TLU_TX_UERR_HDR2_LOG 0x91040 97 #define FO_PCI_TLU_CERR_INT_EN 0xa1008 98 #define FO_PCI_TLU_CERR_INT_STAT 0xa1010 99 #define FO_PCI_TLU_CERR_STAT_CLR 0xa1018 100 #define FO_PCI_LPU_RST 0xe2008 101 #define FO_PCI_LPU_INT_STAT 0xe2040 102 #define FO_PCI_LPU_INT_MASK 0xe0248 103 #define FO_PCI_LPU_LNK_LYR_CFG 0xe2200 104 #define FO_PCI_LPU_LNK_LYR_INT_STAT 0xe2210 105 #define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL 0xe2240 106 #define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS 0xe2400 107 #define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS 0xe2410 108 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR 0xe2430 109 #define FO_PCI_LPU_PHY_LYR_INT_STAT 0xe2610 110 #define FO_PCI_LPU_LTSSM_CFG2 0xe2788 111 #define FO_PCI_LPU_LTSSM_CFG3 0xe2790 112 #define FO_PCI_LPU_LTSSM_CFG4 0xe2798 113 #define FO_PCI_LPU_LTSSM_CFG5 0xe27a0 114 115 /* PCI interrupt mapping registers */ 116 #define FO_PCI_IMAP_MDO_MODE 0x8000000000000000ULL 117 #define FO_PCI_IMAP_V 0x0000000080000000ULL 118 #define FIRE_PCI_IMAP_T_JPID_MASK 0x000000007c000000ULL 119 #define FIRE_PCI_IMAP_T_JPID_SHFT 26 120 #define OBERON_PCI_IMAP_T_DESTID_MASK 0x000000007fe00000ULL 121 #define OBERON_PCI_IMAP_T_DESTID_SHFT 21 122 #define FO_PCI_IMAP_INT_CTRL_NUM_MASK 0x00000000000003c0ULL 123 #define FO_PCI_IMAP_INT_CTRL_NUM_SHFT 6 124 125 /* PCI interrupt clear registers - use INTCLR_* from <machine/bus_common.h> */ 126 127 /* PCI event queue base address register */ 128 #define FO_PCI_EQ_BASE_ADDR_BYPASS 0xfffc000000000000ULL 129 #define FO_PCI_EQ_BASE_ADDR_MASK 0xfffffffffff80000ULL 130 #define FO_PCI_EQ_BASE_ADDR_SHFT 19 131 132 /* PCI event queue control set registers */ 133 #define FO_PCI_EQ_CTRL_SET_ENOVERR 0x0200000000000000ULL 134 #define FO_PCI_EQ_CTRL_SET_EN 0x0000100000000000ULL 135 136 /* PCI event queue control clear registers */ 137 #define FO_PCI_EQ_CTRL_CLR_COVERR 0x0200000000000000ULL 138 #define FO_PCI_EQ_CTRL_CLR_E2I 0x0000800000000000ULL 139 #define FO_PCI_EQ_CTRL_CLR_DIS 0x0000100000000000ULL 140 141 /* PCI event queue tail registers */ 142 #define FO_PCI_EQ_TL_OVERR 0x0200000000000000ULL 143 #define FO_PCI_EQ_TL_MASK 0x000000000000007fULL 144 #define FO_PCI_EQ_TL_SHFT 0 145 146 /* PCI event queue head registers */ 147 #define FO_PCI_EQ_HD_MASK 0x000000000000007fULL 148 #define FO_PCI_EQ_HD_SHFT 0 149 150 /* PCI MSI mapping registers */ 151 #define FO_PCI_MSI_MAP_V 0x8000000000000000ULL 152 #define FO_PCI_MSI_MAP_EQWR_N 0x4000000000000000ULL 153 #define FO_PCI_MSI_MAP_EQNUM_MASK 0x000000000000003fULL 154 #define FO_PCI_MSI_MAP_EQNUM_SHFT 0 155 156 /* PCI MSI clear registers */ 157 #define FO_PCI_MSI_CLR_EQWR_N 0x4000000000000000ULL 158 159 /* 160 * PCI IMU interrupt enable, interrupt status and error status clear 161 * registers 162 */ 163 #define FO_PCI_IMU_ERR_INT_SPARE_S_MASK 0x00007c0000000000ULL 164 #define FO_PCI_IMU_ERR_INT_SPARE_S_SHFT 42 165 #define FO_PCI_IMU_ERR_INT_EQ_OVER_S 0x0000020000000000ULL 166 #define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_S 0x0000010000000000ULL 167 #define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_S 0x0000008000000000ULL 168 #define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_S 0x0000004000000000ULL 169 #define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_S 0x0000002000000000ULL 170 #define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_S 0x0000001000000000ULL 171 #define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_S 0x0000000800000000ULL 172 #define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_S 0x0000000400000000ULL 173 #define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_S 0x0000000200000000ULL 174 #define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_S 0x0000000100000000ULL 175 #define FO_PCI_IMU_ERR_INT_SPARE_P_MASK 0x0000000000007c00ULL 176 #define FO_PCI_IMU_ERR_INT_SPARE_P_SHFT 10 177 #define FO_PCI_IMU_ERR_INT_EQ_OVER_P 0x0000000000000200ULL 178 #define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_P 0x0000000000000100ULL 179 #define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_P 0x0000000000000080ULL 180 #define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_P 0x0000000000000040ULL 181 #define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_P 0x0000000000000020ULL 182 #define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_P 0x0000000000000010ULL 183 #define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_P 0x0000000000000008ULL 184 #define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_P 0x0000000000000004ULL 185 #define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_P 0x0000000000000002ULL 186 #define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_P 0x0000000000000001ULL 187 188 /* PCI IMU RDS error log register */ 189 #define FO_PCI_IMU_RDS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL 190 #define FO_PCI_IMU_RDS_ERR_LOG_TYPE_SHFT 58 191 #define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL 192 #define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_SHFT 48 193 #define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL 194 #define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_SHFT 32 195 #define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL 196 #define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_SHFT 24 197 #define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_MASK 0x0000000000ff0000ULL 198 #define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_SHFT 16 199 #define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_MASK 0x000000000000ffffULL 200 #define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_SHFT 0 201 202 /* PCI IMU SCS error log register */ 203 #define FO_PCI_IMU_SCS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL 204 #define FO_PCI_IMU_SCS_ERR_LOG_TYPE_SHFT 58 205 #define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL 206 #define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_SHFT 48 207 #define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL 208 #define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_SHFT 32 209 #define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL 210 #define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_SHFT 24 211 #define FO_PCI_IMU_SCS_ERR_LOG_BE_MODE_MASK 0x0000000000ff0000ULL 212 #define FO_PCI_IMU_SCS_ERR_LOG_BE_MCODE_SHFT 16 213 #define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL 214 #define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_SHFT 0 215 216 /* PCI IMU EQS error log register */ 217 #define FO_PCI_IMU_EQS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL 218 #define FO_PCI_IMU_EQS_ERROR_LOG_EQ_NUM_SHFT 0 219 220 /* 221 * PCI ERR COR, ERR NONFATAL, ERR FATAL, PM PME and PME To ACK mapping 222 * registers 223 */ 224 #define FO_PCI_ERR_PME_V 0x8000000000000000ULL 225 #define FO_PCI_ERR_PME_EQNUM_MASK 0x000000000000003fULL 226 #define FO_PCI_ERR_PME_EQNUM_SHFT 0 227 228 /* PCI DMC core and block interrupt enable register */ 229 #define FO_PCI_DMC_CORE_BLOCK_INT_EN_DMC 0x8000000000000000ULL 230 #define FO_PCI_DMC_CORE_BLOCK_INT_EN_MMU 0x0000000000000002ULL 231 #define FO_PCI_DMC_CORE_BLOCK_INT_EN_IMU 0x0000000000000001ULL 232 233 /* PCI DMC core and block error status register */ 234 #define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_MMU 0x0000000000000002ULL 235 #define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_IMU 0x0000000000000001ULL 236 237 /* PCI multi core error status register */ 238 #define FO_PCI_MULTI_CORE_ERR_STAT_PEC 0x0000000000000002ULL 239 #define FO_PCI_MULTI_CORE_ERR_STAT_DMC 0x0000000000000001ULL 240 241 /* PCI MSI 32-bit address register */ 242 #define FO_PCI_MSI_32_BIT_ADDR_MASK 0x00000000ffff0000ULL 243 #define FO_PCI_MSI_32_BIT_ADDR_SHFT 16 244 245 /* PCI MSI 64-bit address register */ 246 #define FO_PCI_MSI_64_BIT_ADDR_MASK 0x0000ffffffff0000ULL 247 #define FO_PCI_MSI_64_BIT_ADDR_SHFT 16 248 249 /* 250 * PCI MMU interrupt enable, interrupt status and error status clear 251 * registers 252 */ 253 #define FO_PCI_MMU_ERR_INT_S_MASK 0x0000ffff00000000ULL 254 #define FO_PCI_MMU_ERR_INT_S_SHFT 32 255 #define FO_PCI_MMU_ERR_INT_TBW_DPE_S 0x0000800000000000ULL 256 #define FO_PCI_MMU_ERR_INT_TBW_ERR_S 0x0000400000000000ULL 257 #define FO_PCI_MMU_ERR_INT_TBW_UDE_S 0x0000200000000000ULL 258 #define FO_PCI_MMU_ERR_INT_TBW_DME_S 0x0000100000000000ULL 259 #define FO_PCI_MMU_ERR_INT_SPARE3_S 0x0000080000000000ULL 260 #define FO_PCI_MMU_ERR_INT_SPARE2_S 0x0000040000000000ULL 261 #define FO_PCI_MMU_ERR_INT_TTC_CAE_S 0x0000020000000000ULL 262 #define FIRE_PCI_MMU_ERR_INT_TTC_DPE_S 0x0000010000000000ULL 263 #define OBERON_PCI_MMU_ERR_INT_TTC_DUE_S 0x0000010000000000ULL 264 #define FO_PCI_MMU_ERR_INT_TTE_PRT_S 0x0000008000000000ULL 265 #define FO_PCI_MMU_ERR_INT_TTE_INV_S 0x0000004000000000ULL 266 #define FO_PCI_MMU_ERR_INT_TRN_OOR_S 0x0000002000000000ULL 267 #define FO_PCI_MMU_ERR_INT_TRN_ERR_S 0x0000001000000000ULL 268 #define FO_PCI_MMU_ERR_INT_SPARE1_S 0x0000000800000000ULL 269 #define FO_PCI_MMU_ERR_INT_SPARE0_S 0x0000000400000000ULL 270 #define FO_PCI_MMU_ERR_INT_BYP_OOR_S 0x0000000200000000ULL 271 #define FO_PCI_MMU_ERR_INT_BYP_ERR_S 0x0000000100000000ULL 272 #define FO_PCI_MMU_ERR_INT_P_MASK 0x000000000000ffffULL 273 #define FO_PCI_MMU_ERR_INT_P_SHFT 0 274 #define FO_PCI_MMU_ERR_INT_TBW_DPE_P 0x0000000000008000ULL 275 #define FO_PCI_MMU_ERR_INT_TBW_ERR_P 0x0000000000004000ULL 276 #define FO_PCI_MMU_ERR_INT_TBW_UDE_P 0x0000000000002000ULL 277 #define FO_PCI_MMU_ERR_INT_TBW_DME_P 0x0000000000001000ULL 278 #define FO_PCI_MMU_ERR_INT_SPARE3_P 0x0000000000000800ULL 279 #define FO_PCI_MMU_ERR_INT_SPARE2_P 0x0000000000000400ULL 280 #define FO_PCI_MMU_ERR_INT_TTC_CAE_P 0x0000000000000200ULL 281 #define FIRE_PCI_MMU_ERR_INT_TTC_DPE_P 0x0000000000000100ULL 282 #define OBERON_PCI_MMU_ERR_INT_TTC_DUE_P 0x0000000000000100ULL 283 #define FO_PCI_MMU_ERR_INT_TTE_PRT_P 0x0000000000000080ULL 284 #define FO_PCI_MMU_ERR_INT_TTE_INV_P 0x0000000000000040ULL 285 #define FO_PCI_MMU_ERR_INT_TRN_OOR_P 0x0000000000000020ULL 286 #define FO_PCI_MMU_ERR_INT_TRN_ERR_P 0x0000000000000010ULL 287 #define FO_PCI_MMU_ERR_INT_SPARE1_P 0x0000000000000008ULL 288 #define FO_PCI_MMU_ERR_INT_SPARE0_P 0x0000000000000004ULL 289 #define FO_PCI_MMU_ERR_INT_BYP_OOR_P 0x0000000000000002ULL 290 #define FO_PCI_MMU_ERR_INT_BYP_ERR_P 0x0000000000000001ULL 291 292 /* PCI MMU translation fault address register */ 293 #define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_MASK 0xfffffffffffffffcULL 294 #define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_SHFT 2 295 296 /* PCI MMU translation fault status register */ 297 #define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_MASK 0x000001ff00000000ULL 298 #define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_SHFT 32 299 #define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_MASK 0x00000000007f0000ULL 300 #define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_SHFT 16 301 #define FO_PCI_MMU_TRANS_FAULT_STAT_ID_MASK 0x000000000000ffffULL 302 #define FO_PCI_MMU_TRANS_FAULT_STAT_ID_SHFT 0 303 304 /* 305 * PCI ILU interrupt enable, interrupt status and error status clear 306 * registers 307 */ 308 #define FO_PCI_ILU_ERR_INT_SPARE3_S 0x0000008000000000ULL 309 #define FO_PCI_ILU_ERR_INT_SPARE2_S 0x0000004000000000ULL 310 #define FO_PCI_ILU_ERR_INT_SPARE1_S 0x0000002000000000ULL 311 #define FIRE_PCI_ILU_ERR_INT_IHB_PE_S 0x0000001000000000ULL 312 #define OBERON_PCI_ILU_ERR_INT_IHB_UE_S 0x0000001000000000ULL 313 #define FO_PCI_ILU_ERR_INT_SPARE3_P 0x0000000000000080ULL 314 #define FO_PCI_ILU_ERR_INT_SPARE2_P 0x0000000000000040ULL 315 #define FO_PCI_ILU_ERR_INT_SPARE1_P 0x0000000000000020ULL 316 #define FIRE_PCI_ILU_ERR_INT_IHB_PE_P 0x0000000000000010ULL 317 #define OBERON_PCI_ILU_ERR_INT_IHB_UE_P 0x0000000000000010ULL 318 319 /* PCI DMC debug select registers for port a/b */ 320 #define FO_PCI_DMC_DBG_SEL_PORT_BLCK_MASK 0x00000000000003c0ULL 321 #define FO_PCI_DMC_DBG_SEL_PORT_BLCK_SHFT 6 322 #define FO_PCI_DMC_DBG_SEL_PORT_SUB_MASK 0x0000000000000038ULL 323 #define FO_PCI_DMC_DBG_SEL_PORT_SUB_SHFT 3 324 #define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_MASK 0x0000000000000007ULL 325 #define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_SHFT 0 326 327 /* PCI PEC core and block interrupt enable register */ 328 #define FO_PCI_PEC_CORE_BLOCK_INT_EN_PEC 0x8000000000000000ULL 329 #define FO_PCI_PEC_CORE_BLOCK_INT_EN_ILU 0x0000000000000008ULL 330 #define FO_PCI_PEC_CORE_BLOCK_INT_EN_UERR 0x0000000000000004ULL 331 #define FO_PCI_PEC_CORE_BLOCK_INT_EN_CERR 0x0000000000000002ULL 332 #define FO_PCI_PEC_CORE_BLOCK_INT_EN_OEVENT 0x0000000000000001ULL 333 334 /* PCI PEC core and block interrupt status register */ 335 #define FO_PCI_PEC_CORE_BLOCK_INT_STAT_ILU 0x0000000000000008ULL 336 #define FO_PCI_PEC_CORE_BLOCK_INT_STAT_UERR 0x0000000000000004ULL 337 #define FO_PCI_PEC_CORE_BLOCK_INT_STAT_CERR 0x0000000000000002ULL 338 #define FO_PCI_PEC_CORE_BLOCK_INT_STAT_OEVENT 0x0000000000000001ULL 339 340 /* PCI TLU control register */ 341 #define FO_PCI_TLU_CTRL_L0S_TIM_MASK 0x00000000ff000000ULL 342 #define FO_PCI_TLU_CTRL_L0S_TIM_SHFT 24 343 #define FO_PCI_TLU_CTRL_NWPR_EN 0x0000000000100000ULL 344 #define FO_PCI_TLU_CTRL_CTO_SEL_MASK 0x0000000000070000ULL 345 #define FO_PCI_TLU_CTRL_CTO_SEL_SHFT 16 346 #define FO_PCI_TLU_CTRL_CFG_MASK 0x000000000000ffffULL 347 #define FO_PCI_TLU_CTRL_CFG_SHFT 0 348 #define FO_PCI_TLU_CTRL_CFG_REMAIN_DETECT_QUIET 0x0000000000000100ULL 349 #define FO_PCI_TLU_CTRL_CFG_PAD_LOOPBACK_EN 0x0000000000000080ULL 350 #define FO_PCI_TLU_CTRL_CFG_EWRAP_LOOPBACK_EN 0x0000000000000040ULL 351 #define FO_PCI_TLU_CTRL_CFG_DIGITAL_LOOPBACK_EN 0x0000000000000020ULL 352 #define FO_PCI_TLU_CTRL_CFG_MPS_MASK 0x000000000000001cULL 353 #define FO_PCI_TLU_CTRL_CFG_MPS_SHFT 2 354 #define FO_PCI_TLU_CTRL_CFG_COMMON_CLK_CFG 0x0000000000000002ULL 355 #define FO_PCI_TLU_CTRL_CFG_PORT 0x0000000000000001ULL 356 357 /* 358 * PCI TLU other event interrupt enable, interrupt status and status clear 359 * registers 360 */ 361 #define FO_PCI_TLU_OEVENT_S_MASK 0x00ffffff00000000ULL 362 #define FO_PCI_TLU_OEVENT_S_SHFT 32 363 #define FO_PCI_TLU_OEVENT_SPARE_S 0x0080000000000000ULL 364 #define FO_PCI_TLU_OEVENT_MFC_S 0x0040000000000000ULL 365 #define FO_PCI_TLU_OEVENT_CTO_S 0x0020000000000000ULL 366 #define FO_PCI_TLU_OEVENT_NFP_S 0x0010000000000000ULL 367 #define FO_PCI_TLU_OEVENT_LWC_S 0x0008000000000000ULL 368 #define FO_PCI_TLU_OEVENT_MRC_S 0x0004000000000000ULL 369 #define FO_PCI_TLU_OEVENT_WUC_S 0x0002000000000000ULL 370 #define FO_PCI_TLU_OEVENT_RUC_S 0x0001000000000000ULL 371 #define FO_PCI_TLU_OEVENT_CRS_S 0x0000800000000000ULL 372 #define FO_PCI_TLU_OEVENT_IIP_S 0x0000400000000000ULL 373 #define FO_PCI_TLU_OEVENT_EDP_S 0x0000200000000000ULL 374 #define FIRE_PCI_TLU_OEVENT_EHP_S 0x0000100000000000ULL 375 #define OBERON_PCI_TLU_OEVENT_EHBUE_S 0x0000100000000000ULL 376 #define OBERON_PCI_TLU_OEVENT_EDBUE_S 0x0000100000000000ULL 377 #define FO_PCI_TLU_OEVENT_LIN_S 0x0000080000000000ULL 378 #define FO_PCI_TLU_OEVENT_LRS_S 0x0000040000000000ULL 379 #define FO_PCI_TLU_OEVENT_LDN_S 0x0000020000000000ULL 380 #define FO_PCI_TLU_OEVENT_LUP_S 0x0000010000000000ULL 381 #define FO_PCI_TLU_OEVENT_LPU_S_MASK 0x000000c000000000ULL 382 #define FO_PCI_TLU_OEVENT_LPU_S_SHFT 38 383 #define OBERON_PCI_TLU_OEVENT_TLUEITMO_S 0x0000008000000000ULL 384 #define FO_PCI_TLU_OEVENT_ERU_S 0x0000002000000000ULL 385 #define FO_PCI_TLU_OEVENT_ERO_S 0x0000001000000000ULL 386 #define FO_PCI_TLU_OEVENT_EMP_S 0x0000000800000000ULL 387 #define FO_PCI_TLU_OEVENT_EPE_S 0x0000000400000000ULL 388 #define FIRE_PCI_TLU_OEVENT_ERP_S 0x0000000200000000ULL 389 #define OBERON_PCI_TLU_OEVENT_ERBU_S 0x0000000200000000ULL 390 #define FIRE_PCI_TLU_OEVENT_EIP_S 0x0000000100000000ULL 391 #define OBERON_PCI_TLU_OEVENT_EIUE_S 0x0000000100000000ULL 392 #define FO_PCI_TLU_OEVENT_P_MASK 0x0000000000ffffffULL 393 #define FO_PCI_TLU_OEVENT_P_SHFT 0 394 #define FO_PCI_TLU_OEVENT_SPARE_P 0x0000000000800000ULL 395 #define FO_PCI_TLU_OEVENT_MFC_P 0x0000000000400000ULL 396 #define FO_PCI_TLU_OEVENT_CTO_P 0x0000000000200000ULL 397 #define FO_PCI_TLU_OEVENT_NFP_P 0x0000000000100000ULL 398 #define FO_PCI_TLU_OEVENT_LWC_P 0x0000000000080000ULL 399 #define FO_PCI_TLU_OEVENT_MRC_P 0x0000000000040000ULL 400 #define FO_PCI_TLU_OEVENT_WUC_P 0x0000000000020000ULL 401 #define FO_PCI_TLU_OEVENT_RUC_P 0x0000000000010000ULL 402 #define FO_PCI_TLU_OEVENT_CRS_P 0x0000000000008000ULL 403 #define FO_PCI_TLU_OEVENT_IIP_P 0x0000000000004000ULL 404 #define FO_PCI_TLU_OEVENT_EDP_P 0x0000000000002000ULL 405 #define FIRE_PCI_TLU_OEVENT_EHP_P 0x0000000000001000ULL 406 #define OBERON_PCI_TLU_OEVENT_EHBUE_P 0x0000000000001000ULL 407 #define OBERON_PCI_TLU_OEVENT_EDBUE_P 0x0000000000001000ULL 408 #define FO_PCI_TLU_OEVENT_LIN_P 0x0000000000000800ULL 409 #define FO_PCI_TLU_OEVENT_LRS_P 0x0000000000000400ULL 410 #define FO_PCI_TLU_OEVENT_LDN_P 0x0000000000000200ULL 411 #define FO_PCI_TLU_OEVENT_LUP_P 0x0000000000000100ULL 412 #define FO_PCI_TLU_OEVENT_LPU_P_MASK 0x00000000000000c0ULL 413 #define FO_PCI_TLU_OEVENT_LPU_P_SHFT 6 414 #define OBERON_PCI_TLU_OEVENT_TLUEITMO_P 0x0000000000000080ULL 415 #define FO_PCI_TLU_OEVENT_ERU_P 0x0000000000000020ULL 416 #define FO_PCI_TLU_OEVENT_ERO_P 0x0000000000000010ULL 417 #define FO_PCI_TLU_OEVENT_EMP_P 0x0000000000000008ULL 418 #define FO_PCI_TLU_OEVENT_EPE_P 0x0000000000000004ULL 419 #define FIRE_PCI_TLU_OEVENT_ERP_P 0x0000000000000002ULL 420 #define OBERON_PCI_TLU_OEVENT_ERBU_P 0x0000000000000002ULL 421 #define FIRE_PCI_TLU_OEVENT_EIP_P 0x0000000000000001ULL 422 #define OBERON_PCI_TLU_OEVENT_EIUE_P 0x0000000000000001ULL 423 424 /* PCI receive/transmit DLU/TLU other event header 1/2 log registers */ 425 #define FO_PCI_TLU_OEVENT_HDR_LOG_MASK 0xffffffffffffffffULL 426 #define FO_PCI_TLU_OEVENT_HDR_LOG_SHFT 0 427 428 /* PCI TLU device control register */ 429 #define FO_PCI_TLU_DEV_CTRL_MRRS_MASK 0x0000000000007000ULL 430 #define FO_PCI_TLU_DEV_CTRL_MRRS_SHFT 12 431 #define FO_PCI_TLU_DEV_CTRL_MPS_MASK 0x00000000000000e0ULL 432 #define FO_PCI_TLU_DEV_CTRL_MPS_SHFT 5 433 434 /* 435 * PCI TLU uncorrectable error interrupt enable, interrupt status and 436 * status clear registers 437 */ 438 #define FO_PCI_TLU_UERR_INT_S_MASK 0x001fffff00000000ULL 439 #define FO_PCI_TLU_UERR_INT_S_SHFT 32 440 #define FO_PCI_TLU_UERR_INT_UR_S 0x0010000000000000ULL 441 #define OBERON_PCI_TLU_UERR_INT_ECRC_S 0x0008000000000000ULL 442 #define FO_PCI_TLU_UERR_INT_MFP_S 0x0004000000000000ULL 443 #define FO_PCI_TLU_UERR_INT_ROF_S 0x0002000000000000ULL 444 #define FO_PCI_TLU_UERR_INT_UC_S 0x0001000000000000ULL 445 #define FO_PCI_TLU_UERR_INT_CA_S 0x0000800000000000ULL 446 #define FO_PCI_TLU_UERR_INT_CTO_S 0x0000400000000000ULL 447 #define FO_PCI_TLU_UERR_INT_FCP_S 0x0000200000000000ULL 448 #define FIRE_PCI_TLU_UERR_INT_PP_S 0x0000100000000000ULL 449 #define OBERON_PCI_TLU_UERR_INT_POIS_S 0x0000100000000000ULL 450 #define FO_PCI_TLU_UERR_INT_DLP_S 0x0000001000000000ULL 451 #define FO_PCI_TLU_UERR_INT_TE_S 0x0000000100000000ULL 452 #define FO_PCI_TLU_UERR_INT_P_MASK 0x00000000001fffffULL 453 #define FO_PCI_TLU_UERR_INT_P_SHFT 0 454 #define FO_PCI_TLU_UERR_INT_UR_P 0x0000000000100000ULL 455 #define OBERON_PCI_TLU_UERR_INT_ECRC_P 0x0000000000080000ULL 456 #define FO_PCI_TLU_UERR_INT_MFP_P 0x0000000000040000ULL 457 #define FO_PCI_TLU_UERR_INT_ROF_P 0x0000000000020000ULL 458 #define FO_PCI_TLU_UERR_INT_UC_P 0x0000000000010000ULL 459 #define FO_PCI_TLU_UERR_INT_CA_P 0x0000000000008000ULL 460 #define FO_PCI_TLU_UERR_INT_CTO_P 0x0000000000004000ULL 461 #define FO_PCI_TLU_UERR_INT_FCP_P 0x0000000000002000ULL 462 #define FIRE_PCI_TLU_UERR_INT_PP_P 0x0000000000001000ULL 463 #define OBERON_PCI_TLU_UERR_INT_POIS_P 0x0000000000001000ULL 464 #define FO_PCI_TLU_UERR_INT_DLP_P 0x0000000000000010ULL 465 #define FO_PCI_TLU_UERR_INT_TE_P 0x0000000000000001ULL 466 467 /* 468 * PCI TLU correctable error interrupt enable, interrupt status and 469 * status clear registers 470 */ 471 #define FO_PCI_TLU_CERR_INT_S_MASK 0x001fffff00000000ULL 472 #define FO_PCI_TLU_CERR_INT_S_SHFT 32 473 #define FO_PCI_TLU_CERR_INT_RTO_S 0x0000100000000000ULL 474 #define FO_PCI_TLU_CERR_INT_RNR_S 0x0000010000000000ULL 475 #define FO_PCI_TLU_CERR_INT_BDP_S 0x0000008000000000ULL 476 #define FO_PCI_TLU_CERR_INT_BTP_S 0x0000004000000000ULL 477 #define FO_PCI_TLU_CERR_INT_RE_S 0x0000000100000000ULL 478 #define FO_PCI_TLU_CERR_INT_P_MASK 0x00000000001fffffULL 479 #define FO_PCI_TLU_CERR_INT_P_SHFT 0 480 #define FO_PCI_TLU_CERR_INT_RTO_P 0x0000000000001000ULL 481 #define FO_PCI_TLU_CERR_INT_RNR_P 0x0000000000000100ULL 482 #define FO_PCI_TLU_CERR_INT_BDP_P 0x0000000000000080ULL 483 #define FO_PCI_TLU_CERR_INT_BTP_P 0x0000000000000040ULL 484 #define FO_PCI_TLU_CERR_INT_RE_P 0x0000000000000001ULL 485 486 /* PCI TLU reset register */ 487 #define FO_PCI_LPU_RST_WE 0x0000000080000000ULL 488 #define FO_PCI_LPU_RST_UNUSED_MASK 0x0000000000000e00ULL 489 #define FO_PCI_LPU_RST_UNUSED_SHFT 9 490 #define FO_PCI_LPU_RST_ERR 0x0000000000000100ULL 491 #define FO_PCI_LPU_RST_TXLINK 0x0000000000000080ULL 492 #define FO_PCI_LPU_RST_RXLINK 0x0000000000000040ULL 493 #define FO_PCI_LPU_RST_SMLINK 0x0000000000000020ULL 494 #define FO_PCI_LPU_RST_LTSSM 0x0000000000000010ULL 495 #define FO_PCI_LPU_RST_TXPHY 0x0000000000000008ULL 496 #define FO_PCI_LPU_RST_RXPHY 0x0000000000000004ULL 497 #define FO_PCI_LPU_RST_TXPCS 0x0000000000000002ULL 498 #define FO_PCI_LPU_RST_RXPCS 0x0000000000000001ULL 499 500 /* PCI TLU link control register */ 501 #define FO_PCI_TLU_LNK_CTRL_EXTSYNC 0x0000000000000080ULL 502 #define FO_PCI_TLU_LNK_CTRL_CLK 0x0000000000000040ULL 503 #define FO_PCI_TLU_LNK_CTRL_RETRAIN 0x0000000000000020ULL 504 #define FO_PCI_TLU_LNK_CTRL_DIS 0x0000000000000010ULL 505 #define FO_PCI_TLU_LNK_CTRL_RCB 0x0000000000000008ULL 506 #define FO_PCI_TLU_LNK_CTRL_ASPM_L0S_L1S 0x0000000000000003ULL 507 #define FO_PCI_TLU_LNK_CTRL_ASPM_L1S 0x0000000000000002ULL 508 #define FO_PCI_TLU_LNK_CTRL_ASPM_L0S 0x0000000000000001ULL 509 #define FO_PCI_TLU_LNK_CTRL_ASPM_DIS 0x0000000000000000ULL 510 511 /* PCI TLU link status register */ 512 #define FO_PCI_TLU_LNK_STAT_CLK 0x0000000000001000ULL 513 #define FO_PCI_TLU_LNK_STAT_TRAIN 0x0000000000000800ULL 514 #define FO_PCI_TLU_LNK_STAT_ERR 0x0000000000000400ULL 515 #define FO_PCI_TLU_LNK_STAT_WDTH_MASK 0x00000000000003f0ULL 516 #define FO_PCI_TLU_LNK_STAT_WDTH_SHFT 4 517 #define FO_PCI_TLU_LNK_STAT_SPEED_MASK 0x000000000000000fULL 518 #define FO_PCI_TLU_LNK_STAT_SPEED_SHFT 0 519 520 /* 521 * PCI receive/transmit DLU/TLU uncorrectable error header 1/2 log 522 * registers 523 */ 524 #define FO_PCI_TLU_UERR_HDR_LOG_MASK 0xffffffffffffffffULL 525 #define FO_PCI_TLU_UERR_HDR_LOG_SHFT 0 526 527 /* PCI DLU/LPU interrupt status and mask registers */ 528 #define FO_PCI_LPU_INT_INT 0x0000000080000000ULL 529 #define FIRE_PCI_LPU_INT_PRF_CNT2_OFLW 0x0000000000000080ULL 530 #define FIRE_PCI_LPU_INT_PRF_CNT1_OFLW 0x0000000000000040ULL 531 #define FO_PCI_LPU_INT_LNK_LYR 0x0000000000000020ULL 532 #define FO_PCI_LPU_INT_PHY_ERR 0x0000000000000010ULL 533 #define FIRE_PCI_LPU_INT_LTSSM 0x0000000000000008ULL 534 #define FIRE_PCI_LPU_INT_PHY_TX 0x0000000000000004ULL 535 #define FIRE_PCI_LPU_INT_PHY_RX 0x0000000000000002ULL 536 #define FIRE_PCI_LPU_INT_PHY_GB 0x0000000000000001ULL 537 538 /* PCI DLU/LPU link layer config register */ 539 #define FIRE_PCI_LPU_LNK_LYR_CFG_AUTO_UPDT_DIS 0x0000000000080000ULL 540 #define FIRE_PCI_LPU_LNK_LYR_CFG_FREQ_NAK_EN 0x0000000000040000ULL 541 #define FIRE_PCI_LPU_LNK_LYR_CFG_RPLY_AFTER_REQ 0x0000000000020000ULL 542 #define FIRE_PCI_LPU_LNK_LYR_CFG_LAT_THRS_WR_EN 0x0000000000010000ULL 543 #define FO_PCI_LPU_LNK_LYR_CFG_VC0_EN 0x0000000000000100ULL 544 #define FIRE_PCI_LPU_LNK_LYR_CFG_L0S_ADJ_FAC_EN 0x0000000000000010ULL 545 #define FIER_PCI_LPU_LNK_LYR_CFG_TLP_XMIT_FC_EN 0x0000000000000008ULL 546 #define FO_PCI_LPU_LNK_LYR_CFG_FREQ_ACK_EN 0x0000000000000004ULL 547 #define FO_PCI_LPU_LNK_LYR_CFG_RETRY_DIS 0x0000000000000002ULL 548 549 /* PCI DLU/LPU link layer interrupt and status register */ 550 #define FO_PCI_LPU_LNK_LYR_INT_STAT_LNK_ERR_ACT 0x0000000080000000ULL 551 #define OBERON_PCI_LPU_LNK_LYR_INT_STAT_PBUS_PE 0x0000000000800000ULL 552 #define FO_PCI_LPU_LNK_LYR_INT_STAT_USPRTD_DLLP 0x0000000000400000ULL 553 #define FO_PCI_LPU_LNK_LYR_INT_STAT_DLLP_RX_ERR 0x0000000000200000ULL 554 #define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_DLLP 0x0000000000100000ULL 555 #define FO_PCI_LPU_LNK_LYR_INT_STAT_TLP_RX_ERR 0x0000000000040000ULL 556 #define FO_PCI_LPU_LNK_LYR_INT_STAT_SRC_ERR_TLP 0x0000000000020000ULL 557 #define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_TLP 0x0000000000010000ULL 558 #define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_UDF_ERR 0x0000000000000200ULL 559 #define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_OVF_ERR 0x0000000000000100ULL 560 #define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TLPM_ERR 0x0000000000000080ULL 561 #define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TFRM_ERR 0x0000000000000040ULL 562 #define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_PE 0x0000000000000020ULL 563 #define FO_PCI_LPU_LNK_LYR_INT_STAT_EGRESS_PE 0x0000000000000010ULL 564 #define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_TMR_TO 0x0000000000000004ULL 565 #define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_NUM_RO 0x0000000000000002ULL 566 #define FO_PCI_LPU_LNK_LYR_INT_STAT_DLNK_PES 0x0000000000000001ULL 567 568 /* PCI DLU/LPU flow control update control register */ 569 #define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_C_EN 0x0000000000000004ULL 570 #define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_NP_EN 0x0000000000000002ULL 571 #define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_P_EN 0x0000000000000001ULL 572 573 /* PCI DLU/LPU txlink ACKNAK latency timer threshold register */ 574 #define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_MASK 0x000000000000ffffULL 575 #define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_SHFT 0 576 577 /* PCI DLU/LPU txlink replay timer threshold register */ 578 #define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_MASK 0x00000000000fffffULL 579 #define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_SHFT 0 580 581 /* PCI DLU/LPU txlink FIFO pointer register */ 582 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_MASK 0x00000000ffff0000ULL 583 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_SHFT 16 584 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_MASK 0x000000000000ffffULL 585 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_SHFT 0 586 587 /* PCI DLU/LPU phy layer interrupt and status register */ 588 #define FO_PCI_LPU_PHY_LYR_INT_STAT_PHY_LYR_ERR 0x0000000080000000ULL 589 #define FO_PCI_LPU_PHY_LYR_INT_STAT_KC_DLLP_ERR 0x0000000000000800ULL 590 #define FO_PCI_LPU_PHY_LYR_INT_STAT_END_POS_ERR 0x0000000000000400ULL 591 #define FO_PCI_LPU_PHY_LYR_INT_STAT_LNK_ERR 0x0000000000000200ULL 592 #define FO_PCI_LPU_PHY_LYR_INT_STAT_TRN_ERR 0x0000000000000100ULL 593 #define FO_PCI_LPU_PHY_LYR_INT_STAT_EDB_DET 0x0000000000000080ULL 594 #define FO_PCI_LPU_PHY_LYR_INT_STAT_SDP_END 0x0000000000000040ULL 595 #define FO_PCI_LPU_PHY_LYR_INT_STAT_STP_END_EDB 0x0000000000000020ULL 596 #define FO_PCI_LPU_PHY_LYR_INT_STAT_INVC_ERR 0x0000000000000010ULL 597 #define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_SDP 0x0000000000000008ULL 598 #define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_STP 0x0000000000000004ULL 599 #define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_SDP_POS 0x0000000000000002ULL 600 #define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_STP_POS 0x0000000000000001ULL 601 602 /* PCI DLU/LPU LTSSM config2 register */ 603 #define FO_PCI_LPU_LTSSM_CFG2_12_TO_MASK 0x00000000ffffffffULL 604 #define FO_PCI_LPU_LTSSM_CFG2_12_TO_SHFT 0 605 606 /* PCI DLU/LPU LTSSM config3 register */ 607 #define FO_PCI_LPU_LTSSM_CFG3_2_TO_MASK 0x00000000ffffffffULL 608 #define FO_PCI_LPU_LTSSM_CFG3_2_TO_SHFT 0 609 610 /* PCI DLU/LPU LTSSM config4 register */ 611 #define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_MASK 0x00000000ff000000ULL 612 #define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_SHFT 24 613 #define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_MASK 0x0000000000ff0000ULL 614 #define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_SHFT 16 615 #define FO_PCI_LPU_LTSSM_CFG4_N_FTS_MASK 0x000000000000ff00ULL 616 #define FO_PCI_LPU_LTSSM_CFG4_N_FTS_SHFT 8 617 #define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_MASK 0x00000000000000ffULL 618 #define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_SHFT 0 619 620 /* PCI DLU/LPU LTSSM config5 register */ 621 #define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_MASK 0x00000000ffffe000ULL 622 #define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_SHFT 13 623 #define FO_PCI_LPU_LTSSM_CFG5_RCV_DET_TST_MODE 0x0000000000001000ULL 624 #define FO_PCI_LPU_LTSSM_CFG5_POLL_CMPLNC_DIS 0x0000000000000800ULL 625 #define FO_PCI_LPU_LTSSM_CFG5_TX_IDLE_TX_FTS 0x0000000000000400ULL 626 #define FO_PCI_LPU_LTSSM_CFG5_RX_FTS_RVR_LK 0x0000000000000200ULL 627 #define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_MASK 0x0000000000000180ULL 628 #define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_SHFT 7 629 #define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_ACTIVE 0x0000000000000040ULL 630 #define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_EXIT 0x0000000000000020ULL 631 #define FO_PCI_LPU_LTSSM_CFG5_LPBK_ACTIVE_EXIT 0x0000000000000010ULL 632 #define FO_PCI_LPU_LTSSM_CFG5_L1_IDLE_RCVRY_LK 0x0000000000000008ULL 633 #define FO_PCI_LPU_LTSSM_CFG5_L0_TRN_CNTRL_RST 0x0000000000000004ULL 634 #define FO_PCI_LPU_LTSSM_CFG5_L0_LPBK 0x0000000000000002ULL 635 #define FO_PCI_LPU_LTSSM_CFG5_UNUSED2 0x0000000000000001ULL 636 637 /* Controller configuration and status registers */ 638 #define FIRE_JBUS_PAR_CTRL 0x60010 639 #define FO_XBC_ERR_LOG_EN 0x61000 640 #define FO_XBC_INT_EN 0x61008 641 #define FO_XBC_INT_STAT 0x61010 642 #define FO_XBC_ERR_STAT_CLR 0x61018 643 #define FIRE_JBC_FATAL_RST_EN 0x61028 644 #define FIRE_JBCINT_ITRANS_ERR_LOG 0x61040 645 #define FIRE_JBCINT_ITRANS_ERR_LOG2 0x61048 646 #define FIRE_JBCINT_OTRANS_ERR_LOG 0x61040 647 #define FIRE_JBCINT_OTRANS_ERR_LOG2 0x61048 648 #define FIRE_FATAL_ERR_LOG 0x61050 649 #define FIRE_FATAL_ERR_LOG2 0x61058 650 #define FIRE_MERGE_TRANS_ERR_LOG 0x61060 651 #define FIRE_DMCINT_ODCD_ERR_LOG 0x61068 652 #define FIRE_DMCINT_IDC_ERR_LOG 0x61070 653 #define FIRE_JBC_CSR_ERR_LOG 0x61078 654 #define FIRE_JBC_CORE_BLOCK_INT_EN 0x61800 655 #define FIRE_JBC_CORE_BLOCK_ERR_STAT 0x61808 656 #define FO_XBC_PRF_CNT_SEL 0x62000 657 #define FO_XBC_PRF_CNT0 0x62008 658 #define FO_XBC_PRF_CNT1 0x62010 659 660 /* JBus parity control register */ 661 #define FIRE_JBUS_PAR_CTRL_P_EN 0x8000000000000000ULL 662 #define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_MASK 0x000000000000003cULL 663 #define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_SHFT 2 664 #define FIRE_JBUS_PAR_CTRL_NEXT_DATA 0x0000000000000002ULL 665 #define FIRE_JBUS_PAR_CTRL_NEXT_ADDR 0x0000000000000001ULL 666 667 /* JBC error log enable register - may also apply to UBC */ 668 #define FIRE_JBC_ERR_LOG_EN_SPARE_MASK 0x00000000e0000000ULL 669 #define FIRE_JBC_ERR_LOG_EN_SPARE_SHFT 29 670 #define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP_RD 0x0000000010000000ULL 671 #define FIRE_JBC_ERR_LOG_EN_ILL_ACC_RD 0x0000000008000000ULL 672 #define FIRE_JBC_ERR_LOG_EN_EBUS_TO 0x0000000004000000ULL 673 #define FIRE_JBC_ERR_LOG_EN_MB_PEA 0x0000000002000000ULL 674 #define FIRE_JBC_ERR_LOG_EN_MB_PER 0x0000000001000000ULL 675 #define FIRE_JBC_ERR_LOG_EN_MB_PEW 0x0000000000800000ULL 676 #define FIRE_JBC_ERR_LOG_EN_UE_ASYN 0x0000000000400000ULL 677 #define FIRE_JBC_ERR_LOG_EN_CE_ASYN 0x0000000000200000ULL 678 #define FIRE_JBC_ERR_LOG_EN_JTE 0x0000000000100000ULL 679 #define FIRE_JBC_ERR_LOG_EN_JBE 0x0000000000080000ULL 680 #define FIRE_JBC_ERR_LOG_EN_JUE 0x0000000000040000ULL 681 #define FIRE_JBC_ERR_LOG_EN_IJP 0x0000000000020000ULL 682 #define FIRE_JBC_ERR_LOG_EN_ICISE 0x0000000000010000ULL 683 #define FIRE_JBC_ERR_LOG_EN_CPE 0x0000000000008000ULL 684 #define FIRE_JBC_ERR_LOG_EN_APE 0x0000000000004000ULL 685 #define FIRE_JBC_ERR_LOG_EN_WR_DPE 0x0000000000002000ULL 686 #define FIRE_JBC_ERR_LOG_EN_RD_DPE 0x0000000000001000ULL 687 #define FIRE_JBC_ERR_LOG_EN_ILL_BMW 0x0000000000000800ULL 688 #define FIRE_JBC_ERR_LOG_EN_ILL_BMR 0x0000000000000400ULL 689 #define FIRE_JBC_ERR_LOG_EN_BJC 0x0000000000000200ULL 690 #define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP 0x0000000000000100ULL 691 #define FIRE_JBC_ERR_LOG_EN_PIO_DPE 0x0000000000000080ULL 692 #define FIRE_JBC_ERR_LOG_EN_PIO_CPE 0x0000000000000040ULL 693 #define FIRE_JBC_ERR_LOG_EN_ILL_ACC 0x0000000000000020ULL 694 #define FIRE_JBC_ERR_LOG_EN_UNSOL_RD 0x0000000000000010ULL 695 #define FIRE_JBC_ERR_LOG_EN_UNSOL_INT 0x0000000000000008ULL 696 #define FIRE_JBC_ERR_LOG_EN_JTCEEW 0x0000000000000004ULL 697 #define FIRE_JBC_ERR_LOG_EN_JTCEEI 0x0000000000000002ULL 698 #define FIRE_JBC_ERR_LOG_EN_JTCEER 0x0000000000000001ULL 699 700 /* JBC interrupt enable, interrupt status and error status clear registers */ 701 #define FIRE_JBC_ERR_INT_SPARE_S_MASK 0xe000000000000000ULL 702 #define FIRE_JBC_ERR_INT_SPARE_S_SHFT 61 703 #define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_S 0x1000000000000000ULL 704 #define FIRE_JBC_ERR_INT_ILL_ACC_RD_S 0x0800000000000000ULL 705 #define FIRE_JBC_ERR_INT_EBUS_TO_S 0x0400000000000000ULL 706 #define FIRE_JBC_ERR_INT_MB_PEA_S 0x0200000000000000ULL 707 #define FIRE_JBC_ERR_INT_MB_PER_S 0x0100000000000000ULL 708 #define FIRE_JBC_ERR_INT_MB_PEW_S 0x0080000000000000ULL 709 #define FIRE_JBC_ERR_INT_UE_ASYN_S 0x0040000000000000ULL 710 #define FIRE_JBC_ERR_INT_CE_ASYN_S 0x0020000000000000ULL 711 #define FIRE_JBC_ERR_INT_JTE_S 0x0010000000000000ULL 712 #define FIRE_JBC_ERR_INT_JBE_S 0x0008000000000000ULL 713 #define FIRE_JBC_ERR_INT_JUE_S 0x0004000000000000ULL 714 #define FIRE_JBC_ERR_INT_IJP_S 0x0002000000000000ULL 715 #define FIRE_JBC_ERR_INT_ICISE_S 0x0001000000000000ULL 716 #define FIRE_JBC_ERR_INT_CPE_S 0x0000800000000000ULL 717 #define FIRE_JBC_ERR_INT_APE_S 0x0000400000000000ULL 718 #define FIRE_JBC_ERR_INT_WR_DPE_S 0x0000200000000000ULL 719 #define FIRE_JBC_ERR_INT_RD_DPE_S 0x0000100000000000ULL 720 #define FIRE_JBC_ERR_INT_ILL_BMW_S 0x0000080000000000ULL 721 #define FIRE_JBC_ERR_INT_ILL_BMR_S 0x0000040000000000ULL 722 #define FIRE_JBC_ERR_INT_BJC_S 0x0000020000000000ULL 723 #define FIRE_JBC_ERR_INT_PIO_UNMAP_S 0x0000010000000000ULL 724 #define FIRE_JBC_ERR_INT_PIO_DPE_S 0x0000008000000000ULL 725 #define FIRE_JBC_ERR_INT_PIO_CPE_S 0x0000004000000000ULL 726 #define FIRE_JBC_ERR_INT_ILL_ACC_S 0x0000002000000000ULL 727 #define FIRE_JBC_ERR_INT_UNSOL_RD_S 0x0000001000000000ULL 728 #define FIRE_JBC_ERR_INT_UNSOL_INT_S 0x0000000800000000ULL 729 #define FIRE_JBC_ERR_INT_JTCEEW_S 0x0000000400000000ULL 730 #define FIRE_JBC_ERR_INT_JTCEEI_S 0x0000000200000000ULL 731 #define FIRE_JBC_ERR_INT_JTCEER_S 0x0000000100000000ULL 732 #define FIRE_JBC_ERR_INT_SPARE_P_MASK 0x00000000e0000000ULL 733 #define FIRE_JBC_ERR_INT_SPARE_P_SHFT 29 734 #define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_P 0x0000000010000000ULL 735 #define FIRE_JBC_ERR_INT_ILL_ACC_RD_P 0x0000000008000000ULL 736 #define FIRE_JBC_ERR_INT_EBUS_TO_P 0x0000000004000000ULL 737 #define FIRE_JBC_ERR_INT_MB_PEA_P 0x0000000002000000ULL 738 #define FIRE_JBC_ERR_INT_MB_PER_P 0x0000000001000000ULL 739 #define FIRE_JBC_ERR_INT_MB_PEW_P 0x0000000000800000ULL 740 #define FIRE_JBC_ERR_INT_UE_ASYN_P 0x0000000000400000ULL 741 #define FIRE_JBC_ERR_INT_CE_ASYN_P 0x0000000000200000ULL 742 #define FIRE_JBC_ERR_INT_JTE_P 0x0000000000100000ULL 743 #define FIRE_JBC_ERR_INT_JBE_P 0x0000000000080000ULL 744 #define FIRE_JBC_ERR_INT_JUE_P 0x0000000000040000ULL 745 #define FIRE_JBC_ERR_INT_IJP_P 0x0000000000020000ULL 746 #define FIRE_JBC_ERR_INT_ICISE_P 0x0000000000010000ULL 747 #define FIRE_JBC_ERR_INT_CPE_P 0x0000000000008000ULL 748 #define FIRE_JBC_ERR_INT_APE_P 0x0000000000004000ULL 749 #define FIRE_JBC_ERR_INT_WR_DPE_P 0x0000000000002000ULL 750 #define FIRE_JBC_ERR_INT_RD_DPE_P 0x0000000000001000ULL 751 #define FIRE_JBC_ERR_INT_ILL_BMW_P 0x0000000000000800ULL 752 #define FIRE_JBC_ERR_INT_ILL_BMR_P 0x0000000000000400ULL 753 #define FIRE_JBC_ERR_INT_BJC_P 0x0000000000000200ULL 754 #define FIRE_JBC_ERR_INT_PIO_UNMAP_P 0x0000000000000100ULL 755 #define FIRE_JBC_ERR_INT_PIO_DPE_P 0x0000000000000080ULL 756 #define FIRE_JBC_ERR_INT_PIO_CPE_P 0x0000000000000040ULL 757 #define FIRE_JBC_ERR_INT_ILL_ACC_P 0x0000000000000020ULL 758 #define FIRE_JBC_ERR_INT_UNSOL_RD_P 0x0000000000000010ULL 759 #define FIRE_JBC_ERR_INT_UNSOL_INT_P 0x0000000000000008ULL 760 #define FIRE_JBC_ERR_INT_JTCEEW_P 0x0000000000000004ULL 761 #define FIRE_JBC_ERR_INT_JTCEEI_P 0x0000000000000002ULL 762 #define FIRE_JBC_ERR_INT_JTCEER_P 0x0000000000000001ULL 763 764 /* UBC interrupt enable, error status and error status clear registers */ 765 #define OBERON_UBC_ERR_INT_PIORBEUE_S 0x0004000000000000ULL 766 #define OBERON_UBC_ERR_INT_PIOWBEUE_S 0x0002000000000000ULL 767 #define OBERON_UBC_ERR_INT_PIOWTUE_S 0x0001000000000000ULL 768 #define OBERON_UBC_ERR_INT_MEMWTAXB_S 0x0000080000000000ULL 769 #define OBERON_UBC_ERR_INT_MEMRDAXB_S 0x0000040000000000ULL 770 #define OBERON_UBC_ERR_INT_DMAWTUEB_S 0x0000020000000000ULL 771 #define OBERON_UBC_ERR_INT_DMARDUEB_S 0x0000010000000000ULL 772 #define OBERON_UBC_ERR_INT_MEMWTAXA_S 0x0000000800000000ULL 773 #define OBERON_UBC_ERR_INT_MEMRDAXA_S 0x0000000400000000ULL 774 #define OBERON_UBC_ERR_INT_DMAWTUEA_S 0x0000000200000000ULL 775 #define OBERON_UBC_ERR_INT_DMARDUEA_S 0x0000000100000000ULL 776 #define OBERON_UBC_ERR_INT_PIORBEUE_P 0x0000000000040000ULL 777 #define OBERON_UBC_ERR_INT_PIOWBEUE_P 0x0000000000020000ULL 778 #define OBERON_UBC_ERR_INT_PIOWTUE_P 0x0000000000010000ULL 779 #define OBERON_UBC_ERR_INT_MEMWTAXB_P 0x0000000000000800ULL 780 #define OBERON_UBC_ERR_INT_MEMRDAXB_P 0x0000000000000400ULL 781 #define OBERON_UBC_ERR_INT_DMARDUEB_P 0x0000000000000200ULL 782 #define OBERON_UBC_ERR_INT_DMAWTUEB_P 0x0000000000000100ULL 783 #define OBERON_UBC_ERR_INT_MEMWTAXA_P 0x0000000000000008ULL 784 #define OBERON_UBC_ERR_INT_MEMRDAXA_P 0x0000000000000004ULL 785 #define OBERON_UBC_ERR_INT_DMAWTUEA_P 0x0000000000000002ULL 786 #define OBERON_UBC_ERR_INT_DMARDUEA_P 0x0000000000000001ULL 787 788 /* JBC fatal reset enable register */ 789 #define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_MASK 0x000000000c000000ULL 790 #define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_SHFT 26 791 #define FIRE_JBC_FATAL_RST_EN_MB_PEA_P_INT 0x0000000002000000ULL 792 #define FIRE_JBC_FATAL_RST_EN_CPE_P_INT 0x0000000000008000ULL 793 #define FIRE_JBC_FATAL_RST_EN_APE_P_INT 0x0000000000004000ULL 794 #define FIRE_JBC_FATAL_RST_EN_PIO_CPE_INT 0x0000000000000040ULL 795 #define FIRE_JBC_FATAL_RST_EN_JTCEEW_P_INT 0x0000000000000004ULL 796 #define FIRE_JBC_FATAL_RST_EN_JTCEEI_P_INT 0x0000000000000002ULL 797 #define FIRE_JBC_FATAL_RST_EN_JTCEER_P_INT 0x0000000000000001ULL 798 799 /* JBC JBCINT in transaction error log register */ 800 #define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL 801 #define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_SHFT 54 802 #define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL 803 #define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_SHFT 48 804 #define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 805 #define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_SHFT 0 806 807 /* JBC JBCINT in transaction error log register 2 */ 808 #define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 809 #define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_SHFT 28 810 #define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 811 #define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_SHFT 21 812 #define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 813 #define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_SHFT 0 814 815 /* JBC JBCINT out transaction error log register */ 816 #define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_MASK 0x003f000000000000ULL 817 #define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_SHFT 48 818 #define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 819 #define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_SHFT 0 820 821 /* JBC JBCINT out transaction error log register 2 */ 822 #define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 823 #define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_SHFT 28 824 #define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 825 #define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_SHFT 21 826 #define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 827 #define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_SHFT 0 828 829 /* JBC merge transaction error log register */ 830 #define FIRE_FATAL_ERR_LOG_DATA_MASK 0xffffffffffffffffULL 831 #define FIRE_FATAL_ERR_LOG_DATA_SHFT 0 832 833 /* JBC merge transaction error log register 2 */ 834 #define FIRE_FATAL_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 835 #define FIRE_FATAL_ERR_LOG2_ARB_WN_SHFT 28 836 #define FIRE_FATAL_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 837 #define FIRE_FATAL_ERR_LOG2_J_REQ_SHFT 21 838 #define FIRE_FATAL_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 839 #define FIRE_FATAL_ERR_LOG2_J_PACK_SHFT 0 840 841 /* JBC merge transaction error log register */ 842 #define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL 843 #define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_SHFT 54 844 #define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL 845 #define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_SHFT 48 846 #define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_MASK 0x0000f80000000000ULL 847 #define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_SHFT 43 848 #define FIRE_MERGE_TRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 849 #define FIRE_MERGE_TRANS_ERR_LOG_ADDR_SHFT 0 850 851 /* JBC DMCINT ODCD error log register */ 852 #define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_MASK 0x0030000000000000ULL 853 #define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_SHFT 52 854 #define FIRE_DMCINT_ODCD_ERR_LOG_AID_MASK 0x000f000000000000ULL 855 #define FIRE_DMCINT_ODCD_ERR_LOG_AID_SHFT 48 856 #define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_MASK 0x0000f80000000000ULL 857 #define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_SHFT 43 858 #define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 859 #define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_SHFT 0 860 861 /* JBC DMCINT IDC error log register */ 862 #define FIRE_DMCINT_IDC_ERR_DMC_CTAG_MASK 0x000000000fff0000ULL 863 #define FIRE_DMCINT_IDC_ERR_DMC_CTAG_SHFT 16 864 #define FIRE_DMCINT_IDC_ERR_TRANSID_MASK 0x000000000000c000ULL 865 #define FIRE_DMCINT_IDC_ERR_AGNTID_MASK 0x0000000000003c00ULL 866 #define FIRE_DMCINT_IDC_ERR_AGNTID_SHFT 10 867 #define FIRE_DMCINT_IDC_ERR_SRCID_MASK 0x00000000000003e0ULL 868 #define FIRE_DMCINT_IDC_ERR_SRCID_SHFT 5 869 #define FIRE_DMCINT_IDC_ERR_TARGID_MASK 0x000000000000001fULL 870 #define FIRE_DMCINT_IDC_ERRO_TARGID_SHFT 0 871 872 /* JBC CSR error log register */ 873 #define FIRE_JBC_CSR_ERR_LOG_WR 0x0000040000000000ULL 874 #define FIRE_JBC_CSR_ERR_LOG_BMASK_MASK 0x000003fffc000000ULL 875 #define FIRE_JBC_CSR_ERR_LOG_BMASK_SHFT 26 876 #define FIRE_JBC_CSR_ERR_LOG_ADDR_MASK 0x0000000003ffffffULL 877 #define FIRE_JBC_CSR_ERR_LOG_ADDR_SHFT 0 878 879 /* JBC core and block interrupt enable register */ 880 #define FIRE_JBC_CORE_BLOCK_INT_EN_JBC 0x8000000000000000ULL 881 #define FIRE_JBC_CORE_BLOCK_INT_EN_CSR 0x0000000000000008ULL 882 #define FIRE_JBC_CORE_BLOCK_INT_EN_MERGE 0x0000000000000004ULL 883 #define FIRE_JBC_CORE_BLOCK_INT_EN_JBCINT 0x0000000000000002ULL 884 #define FIRE_JBC_CORE_BLOCK_INT_EN_DMCINT 0x0000000000000001ULL 885 886 /* JBC core and block error status register */ 887 #define FIRE_JBC_CORE_BLOCK_ERR_STAT_CSR 0x0000000000000008ULL 888 #define FIRE_JBC_CORE_BLOCK_ERR_STAT_MERGE 0x0000000000000004ULL 889 #define FIRE_JBC_CORE_BLOCK_ERR_STAT_JBCINT 0x0000000000000002ULL 890 #define FIRE_JBC_CORE_BLOCK_ERR_STAT_DMCINT 0x0000000000000001ULL 891 892 /* JBC performance counter select register - may also apply to UBC */ 893 #define FO_XBC_PRF_CNT_PIO_RD_PCIEB 0x0000000000000018ULL 894 #define FO_XBC_PRF_CNT_PIO_WR_PCIEB 0x0000000000000017ULL 895 #define FO_XBC_PRF_CNT_PIO_RD_PCIEA 0x0000000000000016ULL 896 #define FO_XBC_PRF_CNT_PIO_WR_PCIEA 0x0000000000000015ULL 897 #define FO_XBC_PRF_CNT_WB 0x0000000000000014ULL 898 #define FO_XBC_PRF_CNT_PIO_FRGN 0x0000000000000013ULL 899 #define FO_XBC_PRF_CNT_XB_NCHRNT 0x0000000000000012ULL 900 #define FO_XBC_PRF_CNT_FO_CHRNT 0x0000000000000011ULL 901 #define FO_XBC_PRF_CNT_XB_CHRNT 0x0000000000000010ULL 902 #define FO_XBC_PRF_CNT_AOKOFF_DOKOFF 0x000000000000000fULL 903 #define FO_XBC_PRF_CNT_DOKOFF 0x000000000000000eULL 904 #define FO_XBC_PRF_CNT_AOKOFF 0x000000000000000dULL 905 #define FO_XBC_PRF_CNT_RD_TOTAL 0x000000000000000cULL 906 #define FO_XBC_PRF_CNT_WR_TOTAL 0x000000000000000bULL 907 #define FO_XBC_PRF_CNT_WR_PARTIAL 0x000000000000000aULL 908 #define FO_XBC_PRF_CNT_PIOS_CSR_RINGB 0x0000000000000009ULL 909 #define FO_XBC_PRF_CNT_PIOS_CSR_RINGA 0x0000000000000008ULL 910 #define FO_XBC_PRF_CNT_PIOS_EBUS 0x0000000000000007ULL 911 #define FO_XBC_PRF_CNT_PIOS_I2C 0x0000000000000006ULL 912 #define FO_XBC_PRF_CNT_RD_LAT_SMPLS 0x0000000000000005ULL 913 #define FO_XBC_PRF_CNT_RD_LAT 0x0000000000000004ULL 914 #define FO_XBC_PRF_CNT_ON_XB 0x0000000000000003ULL 915 #define FO_XBC_PRF_CNT_XB_IDL 0x0000000000000002ULL 916 #define FO_XBC_PRF_CNT_XB_CLK 0x0000000000000001ULL 917 #define FO_XBC_PRF_CNT_NONE 0x0000000000000000ULL 918 #define FO_XBC_PRF_CNT_CNT1_SHFT 8 919 #define FO_XBC_PRF_CNT_CNT0_SHFT 0 920 921 /* JBC performance counter 0/1 registers - may also apply to UBC */ 922 #define FO_XBC_PRF_CNT_MASK 0xffffffffffffffffULL 923 #define FO_XBC_PRF_CNT_SHFT 0 924 925 /* Lookup tables */ 926 const uint16_t fire_freq_nak_tmr_thrs[6][4] = { 927 { 0x00ed, 0x049, 0x043, 0x030 }, 928 { 0x01a0, 0x076, 0x06b, 0x048 }, 929 { 0x022f, 0x09a, 0x056, 0x056 }, 930 { 0x042f, 0x11a, 0x096, 0x096 }, 931 { 0x082f, 0x21a, 0x116, 0x116 }, 932 { 0x102f, 0x41a, 0x216, 0x216 } 933 }; 934 935 const uint16_t fire_rply_tmr_thrs[6][4] = { 936 { 0x0379, 0x112, 0x0fc, 0x0b4 }, 937 { 0x0618, 0x1BA, 0x192, 0x10e }, 938 { 0x0831, 0x242, 0x143, 0x143 }, 939 { 0x0fb1, 0x422, 0x233, 0x233 }, 940 { 0x1eb0, 0x7e1, 0x412, 0x412 }, 941 { 0x3cb0, 0xf61, 0x7d2, 0x7d2 } 942 }; 943 944 /* Register default values */ 945 #define FO_PCI_TLU_CTRL_L0S_TIM_DFLT 0xda 946 #define FO_PCI_TLU_CTRL_CFG_DFLT 0x1 947 #define FO_PCI_LPU_LTSSM_CFG2_12_TO_DFLT 0x2dc6c0 948 #define FO_PCI_LPU_LTSSM_CFG3_2_TO_DFLT 0x7a120 949 #define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_DFLT 0x2 950 #define FO_PCI_LPU_LTSSM_CFG4_N_FTS_DFLT 0x8c 951 #define OBERON_PCI_LPU_TXLNK_RPLY_TMR_THRS_DFLT 0xc9 952 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_DFLT 0x0 953 #define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_DFLT 0xffff 954 955 /* INO macros */ 956 #define FO_EQ_FIRST_INO 0x18 957 #define FO_EQ_LAST_INO 0x3b 958 #define FO_DMC_PEC_INO 0x3e 959 #define FO_XCB_INO 0x3f 960 #define FO_MAX_INO FO_XCB_INO 961 962 /* Device space macros */ 963 #define FO_CONF_BUS_SHFT 20 964 #define FO_CONF_DEV_SHFT 15 965 #define FO_CONF_FUNC_SHFT 12 966 #define FO_CONF_REG_SHFT 0 967 #define FO_IO_SIZE 0x10000000 968 #define FO_MEM_SIZE 0x1ffff0000 969 970 #define FO_CONF_OFF(bus, slot, func, reg) \ 971 (((bus) << FO_CONF_BUS_SHFT) | \ 972 ((slot) << FO_CONF_DEV_SHFT) | \ 973 ((func) << FO_CONF_FUNC_SHFT) | \ 974 ((reg) << FO_CONF_REG_SHFT)) 975 976 /* Width of the physical addresses the IOMMU translates to */ 977 #define FIRE_IOMMU_BITS 43 978 #define OBERON_IOMMU_BITS 47 979 980 /* Event queue macros */ 981 #define FO_EQ_ALIGNMENT (512 * 1024) 982 #define FO_EQ_NRECORDS 128 983 #define FO_EQ_RECORD_SIZE 64 984 985 /* Event queue record format */ 986 struct fo_msiq_record { 987 uint64_t fomqr_word0; 988 uint64_t fomqr_word1; 989 uint64_t fomqr_reserved[6]; 990 }; 991 992 #define FO_MQR_WORD0_FMT_TYPE_MASK 0x7f00000000000000ULL 993 #define FO_MQR_WORD0_FMT_TYPE_SHFT 56 994 #define FO_MQR_WORD0_FMT_TYPE_MSI64 0x7800000000000000ULL 995 #define FO_MQR_WORD0_FMT_TYPE_MSI32 0x5800000000000000ULL 996 #define FO_MQR_WORD0_FMT_TYPE_MSG 0x3000000000000000ULL 997 #define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_MASK 0x0700000000000000ULL 998 #define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_SHFT 56 999 #define FO_MQR_WORD0_LENGTH_MASK 0x00ffc00000000000ULL 1000 #define FO_MQR_WORD0_LENGTH_SHFT 46 1001 #define FO_MQR_WORD0_ADDR0_MASK 0x00003fff00000000ULL 1002 #define FO_MQR_WORD0_ADDR0_SHFT 32 1003 #define FO_MQR_WORD0_RID_MASK 0x00000000ffff0000ULL 1004 #define FO_MQR_WORD0_RID_SHFT 16 1005 #define FO_MQR_WORD0_DATA0_MASK 0x000000000000ffffULL 1006 #define FO_MQR_WORD0_DATA0_SHFT 0 1007 #define FO_MQR_WORD1_ADDR1_MASK 0xffffffffffff0000ULL 1008 #define FO_MQR_WORD1_ADDR1_SHFT 16 1009 #define FO_MQR_WORD1_DATA1_MASK 0x000000000000ffffULL 1010 #define FO_MQR_WORD1_DATA1_SHFT 0 1011 1012 #endif /* !_SPARC64_PCI_FIREREG_H_ */ 1013