| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 89 DAG_FUNCTION(nearbyint, 1, 1, experimental_constrained_nearbyint, FNEARBYINT)
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 882 FNEARBYINT, enumerator
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| D | BasicTTIImpl.h | 1617 ISDs.push_back(ISD::FNEARBYINT); in getTypeBasedIntrinsicInstrCost()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 505 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
603 Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 299 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
814 setOperationAction(ISD::FNEARBYINT, VT, Expand); in PPCTargetLowering()
876 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
967 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
968 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
974 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
980 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1175 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 211 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 102 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
1226 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
2241 case ISD::FNEARBYINT: in PromoteFloatResult()
2605 case ISD::FNEARBYINT: in SoftPromoteHalfResult()
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| D | LegalizeVectorOps.cpp | 428 case ISD::FNEARBYINT: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 90 case ISD::FNEARBYINT: in ScalarizeVectorResult()
984 case ISD::FNEARBYINT: in SplitVectorResult()
3119 case ISD::FNEARBYINT: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 4013 case ISD::FNEARBYINT: in ConvertNodeToLibcall()
4719 case ISD::FNEARBYINT: in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 6266 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in visitIntrinsicCall()
8008 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) in visitCall()
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| D | SelectionDAG.cpp | 4356 case ISD::FNEARBYINT: { in isKnownNeverNaN()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 343 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); in AMDGPUTargetLowering()
344 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); in AMDGPUTargetLowering()
521 setOperationAction(ISD::FNEARBYINT, VT, Expand); in AMDGPUTargetLowering()
645 case ISD::FNEARBYINT: in fnegFoldsIntoOp()
1295 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
3915 case ISD::FNEARBYINT: // XXX - Should fround be handled? in performFNegCombine()
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| D | AMDGPUISelDAGToDAG.cpp | 436 case ISD::FNEARBYINT: in fp16SrcZerosHighBits()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 629 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in AArch64TargetLowering()
663 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); in AArch64TargetLowering()
674 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); in AArch64TargetLowering()
692 setOperationAction(ISD::FNEARBYINT, Ty, Legal); in AArch64TargetLowering()
709 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal); in AArch64TargetLowering()
976 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand); in AArch64TargetLowering()
1117 setOperationAction(ISD::FNEARBYINT, Ty, Legal); in AArch64TargetLowering()
1128 setOperationAction(ISD::FNEARBYINT, Ty, Legal); in AArch64TargetLowering()
1280 setOperationAction(ISD::FNEARBYINT, VT, Custom); in AArch64TargetLowering()
1540 setOperationAction(ISD::FNEARBYINT, VT, Custom); in addTypeForFixedLengthSVE()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 895 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 125 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1074 case ISD::FNEARBYINT: in PreprocessISelDAG()
1092 case ISD::FNEARBYINT: Imm = 0xC; break; in PreprocessISelDAG()
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| D | X86ISelLowering.cpp | 709 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); in X86TargetLowering()
834 setOperationAction(ISD::FNEARBYINT, VT, Expand); in X86TargetLowering()
1132 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal); in X86TargetLowering()
1234 setOperationAction(ISD::FNEARBYINT, VT, Legal); in X86TargetLowering()
1621 setOperationAction(ISD::FNEARBYINT, VT, Legal); in X86TargetLowering()
41083 case ISD::FNEARBYINT: in scalarizeExtEltFP()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 457 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
514 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in SystemZTargetLowering()
546 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 489 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 365 setOperationAction(ISD::FNEARBYINT, VT, Expand); in addMVEVectorTypes()
851 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
871 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
887 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
1035 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
1448 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1464 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1644 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 145 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 533 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in NVPTXTargetLowering()
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